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| parallel nor flash embedded memory jr28f032m29ewxx; pz28f032m29ewxx; js28f064m29ewxx pc28f064m29ewxx; jr28f064m29ewxx; pz28f064m29ewxx js28f128m29ewxx; pc28f128m29ewxx; rc28f128m29ewxx featur es ? s upply v oltage C v c c = 2.7C3.6v (pr ogr am, er ase , r ead) C v c c q = 1.65C3.6v (i/o buffers) ? asynchr onous r andom or page r ead C p age siz e: 8 wor ds or 16 b ytes C p age access: 25ns C r andom access: 60ns (bga); 70ns ( t sop) ? b uffer pr ogr am: 256-wor d ma x pr ogr am buffer ? p r ogr am time C 0.56s per b yte (1.8 mb/s t yp when using 256- wor d buffer siz e in buffer pr ogr am without v pp h ) C 0.31s per b yte (3.2 mb/s t yp when using 256- wor d buffer siz e in buffer pr ogr am with v pp h ) ? m emor y or ganization C 32mb: 64 main blocks , 64kb each, or eight 8kb boot blocks (top or bottom) and 63 main blocks , 64kb each C 64mb: 128 main blocks , 64kb each, or eight 8kb boot blocks (top or bottom) and 127 main blocks , 64 kb each C 128mb: 128 main blocks , 128kb each ? p r ogr am/er ase contr oller C e mbedded b yte/wor d pr ogr am algor ithms ? p r ogr am/er ase suspend and r esume capability C read oper ation on any block dur ing a pr o- gram susp end oper ation C read or pr ogram oper ation on one block dur - ing an erase susp end oper ation on another block ? bl ank check oper ation to v er ify an er ased block ? u nlock b ypass , block er ase , chip er ase , and wr ite to buffer capability C f ast buffer ed/batch pr ogr amming C f ast block and chip er ase ? v pp /wp# pin pr otection C v pp h v oltage on v pp to acceler ate pr ogr amming per for mance C p r otects highest/lo w est block (h/l unifor m) or top/bottom two blocks ( t/b boot) ? s oftwar e pr otection C v olatile pr otection C n onv olatile pr otection C p asswor d pr otection C p asswor d access ? e xtended memor y block C 128-wor d (256-b yte) block for per manent secur e identification C p r ogr am or lock implemented at the factor y or b y the customer ? lo w-po w er consumption: s tandb y mode ? jesd47h-compliant C 100,000 minimum erase cy cles per block C d ata r etention: 20 y ears ( t yp) ? 65nm single-bit cell pr ocess technology ? p ackages ( jedec-standar d) C 56-pin t sop (128mb , 64mb) C 48-pin t sop (64mb , 32mb) C 64-ball fbga (128mb , 64mb) C 48-ball bga (64mb , 32mb) ? g r een packages av ailable C r ohs-compliant C h alogen-fr ee ? o per ating temper atur e C ambient: C40c to +85c 32mb, 64mb, 128mb: 3v embedded parallel nor flash features pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 1 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron t echnology , inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice. http://
part numbering information this pr oduct is av ailable with the pr elocked extended memor y block. d evices ar e shipped fr om the factor y with memory content bits erased to 1. for a list of available options, such as packages or high/low protection, or for further information, contact your micron sales representative. table 1: part number information part number category category details package js = 56-pin tsop, 14mm x 20mm, lead-free, halogen-free, rohs-compliant pc = 64-ball fortified bga, 11mm x 13mm, lead-free, halogen-free, rohs-compliant rc = 64-ball fortified bga, 11mm x 13mm, leaded jr = 48-pin tsop, 12mm x 20mm, lead-free, halogen-free, rohs-compliant pz = 48-ball bga, 6mm x 8mm, lead-free, halogen-free, rohs-compliant product designator 28f = parallel nor interface density 128 = 128mb 064 = 64mb 032 = 32mb device type m29ew = embedded flash memory (3v core, page read) device function h = highest block protected by v pp /wp#; uniform block l = lowest block protected by v pp /wp#; uniform block b = bottom boot; bottom two blocks protected by v pp /wp# t = top boot; top two blocks protected by v pp /wp# features a/b/f/x or an asterisk (*) = combination of features, including packing media, security features, and specific customer request information valid m29ew part number combinations table 2: standard part numbers by density, medium, and package density medium package js pc rc jr pz 32mb tray C C C jr28f032m29ewha pz28f032m29ewha jr28f032m29ewla pz28f032m29ewla jr28f032m29ewba pz28f032m29ewba jr28f032m29ewta pz28f032m29ewta tape and reel C C C jr28f032m29ewbb pz28f032m29ewbb jr28f032m29ewtb 32mb, 64mb, 128mb: 3v embedded parallel nor flash features pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 2 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 2: standard part numbers by density, medium, and package (continued) density medium package js pc rc jr pz 64mb tray JS28F064M29EWHA pc28f064m29ewha C jr28f064m29ewha pz28f064m29ewha js28f064m29ewla pc28f064m29ewla jr28f064m29ewla pz28f064m29ewla js28f064m29ewba pc28f064m29ewba jr28f064m29ewba pz28f064m29ewba js28f064m29ewta pc28f064m29ewta jr28f064m29ewta pz28f064m29ewta tape and reel js28f064m29ewlb C C jr28f064m29ewhb pz28f064m29ewbb jr28f064m29ewlb jr28f064m29ewtb 128mb tray js28f128m29ewhf pc28f128m29ewhf rc28f128m29ewhf C C js28f128m29ewla pc28f128m29ewla rc28f128m29ewla tape and reel C C C C C table 3: part numbers with security features by density, medium, and package density medium package pc pz 64mb tray pc28f064m29ewhx pz28f064m29ewhx pc28f064m29ewlx pz28f064m29ewlx pc28f064m29ewbx pz28f064m29ewbx pc28f064m29ewtx pz28f064m29ewtx tape and reel pc28f064m29ewty C 128mb tray pc28f128m29ewhx C pc28f128m29ewlx tape and reel C C note: 1. this data sheet covers only standard parts. for security parts, contact your local micron sales representative. 32mb, 64mb, 128mb: 3v embedded parallel nor flash features pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 3 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. contents g ener al d escr iption ......................................................................................................................................... 8 s ignal assignments ........................................................................................................................................... 9 s ignal d escr iptions ......................................................................................................................................... 13 m emor y or ganization .................................................................................................................................... 14 m emor y c onfigur ation ............................................................................................................................... 14 m emor y m ap C 32mb ................................................................................................................................. 15 m emor y m ap C 64mb ................................................................................................................................. 17 m emor y m ap C 128mb ................................................................................................................................ 19 b us o per ations ............................................................................................................................................... 20 r ead .......................................................................................................................................................... 20 w r ite .......................................................................................................................................................... 20 s tandb y ..................................................................................................................................................... 20 o utput d isable ........................................................................................................................................... 21 r eset .......................................................................................................................................................... 21 r egisters ........................................................................................................................................................ 22 s tatus r egister ............................................................................................................................................ 22 lock r egister .............................................................................................................................................. 27 s tandar d c ommand d efinitions C a ddr ess-d ata c y cles .................................................................................... 30 read and a ut o select o per ations .............................................................................................................. 33 read/reset c ommand ............................................................................................................................ 33 read cfi c ommand .................................................................................................................................. 33 a ut o select c ommand ........................................................................................................................... 33 b ypass o per ations .......................................................................................................................................... 35 unl ock byp ass c ommand ...................................................................................................................... 35 unl ock byp ass reset c ommand ............................................................................................................ 36 p r ogr am o per ations ....................................................................................................................................... 36 pr ogram c ommand ................................................................................................................................ 36 unl ock byp ass pr ogram c ommand ..................................................................................................... 37 double by te/w ord pr ogram c ommand ............................................................................................. 37 q u adr uple by te/w ord pr ogram c ommand ...................................................................................... 37 octuple by te pr ogram c ommand ....................................................................................................... 38 write t o b uffer pr ogram c ommand .................................................................................................. 38 unl ock byp ass write t o b uffer pr ogram c ommand ....................................................................... 40 enhanced write t o b uffer pr ogram c ommand ............................................................................... 41 unl ock byp ass enhanced write t o b uffer pr ogram c ommand ................................................... 41 write t o b uffer pr ogram c onfirm c ommand .................................................................................. 42 enhanced write t o b uffer pr ogram c onfirm c ommand .............................................................. 42 b uffered pr ogram abor t and reset c ommand ................................................................................ 42 pr ogram susp end c ommand ................................................................................................................ 42 pr ogram resume c ommand .................................................................................................................. 43 e r ase o per ations ............................................................................................................................................ 43 chip erase c ommand .............................................................................................................................. 43 unl ock byp ass chip erase c ommand ................................................................................................... 43 bl ock erase c ommand ........................................................................................................................... 44 unl ock byp ass bl ock erase c ommand ................................................................................................ 44 erase susp end c ommand ....................................................................................................................... 44 erase resume c ommand ........................................................................................................................ 45 bl ank check o per ation .............................................................................................................................. 45 bl ank check c ommands ........................................................................................................................ 45 block protection command definitions C address-data cycles ........................................................................ 47 32mb, 64mb, 128mb: 3v embedded parallel nor flash features pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 4 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. p r otection o per ations .................................................................................................................................... 50 l ock register c ommands ...................................................................................................................... 50 p assw ord pr o tection c ommands ....................................................................................................... 50 nonv ol a tile pr o tection c ommands .................................................................................................. 50 nonv ol a tile pr o tection bit l ock bit c ommands ............................................................................ 53 v ol a tile pr o tection c ommands .......................................................................................................... 53 extended memor y bl ock c ommands .................................................................................................. 53 exit pr o tection c ommand .................................................................................................................... 54 d evice p r otection ........................................................................................................................................... 55 h ar dwar e p r otection .................................................................................................................................. 55 s oftwar e p r otection .................................................................................................................................... 55 v olatile p r otection m ode ............................................................................................................................. 56 n onv olatile p r otection m ode ...................................................................................................................... 56 p asswor d p r otection m ode .......................................................................................................................... 57 p asswor d a ccess ......................................................................................................................................... 57 c ommon f lash i nter face ................................................................................................................................ 59 p o w er -u p and r eset char acter istics ................................................................................................................ 64 a bsolute r atings and o per ating c onditions ..................................................................................................... 66 dc char acter istics .......................................................................................................................................... 68 r ead a c char acter istics .................................................................................................................................. 70 w r ite a c char acter istics ................................................................................................................................. 73 a cceler ated p r ogr am, d ata p olling/t oggle a c char acter istics ........................................................................... 80 e lectr ical s pecifications C p r ogr am/e r ase char acter istics ................................................................................. 82 p ackage d imensions ....................................................................................................................................... 83 r evision h istor y ............................................................................................................................................. 87 r ev . b C 11/12 ............................................................................................................................................. 87 rev. a C 08/12 ............................................................................................................................................. 87 32mb, 64mb, 128mb: 3v embedded parallel nor flash features pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 5 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. list of figur es f igur e 1: logic d iagr am ................................................................................................................................... 8 f igur e 2: 56-pin t sop ( t op v iew) .................................................................................................................... 9 f igur e 3: 48-pin t sop ( t op v iew) .................................................................................................................. 10 f igur e 4: 48-b all bga ( t op and b ottom v iews) ............................................................................................... 11 f igur e 5: 64-b all f or tified bga ( t op and b ottom v iews) .................................................................................. 12 f igur e 6: d ata p olling f lo w char t .................................................................................................................... 24 f igur e 7: t oggle b it f lo w char t ........................................................................................................................ 25 f igur e 8: s tatus r egister p olling f lo w char t ..................................................................................................... 26 f igur e 9: lock r egister p r ogr am f lo w char t ..................................................................................................... 28 f igur e 10: b oundar y c ondition of p r ogr am b uffer s iz e .................................................................................... 39 f igur e 11: write t o b uffer pr ogram f lo w char t ...................................................................................... 40 f igur e 12: p r ogr am/e r ase n onv olatile p r otection b it algor ithm ...................................................................... 52 f igur e 13: s oftwar e p r otection scheme .......................................................................................................... 57 f igur e 14: p o w er -u p t iming .......................................................................................................................... 64 f igur e 15: r eset a c t iming C n o pr ogram/erase o per ation in p r ogr ess ...................................................... 65 f igur e 16: r eset a c t iming d ur ing pr ogram/erase o per ation .................................................................... 65 f igur e 17: a c m easur ement load cir cuit ....................................................................................................... 67 f igur e 18: a c m easur ement i/o w av efor m ..................................................................................................... 67 f igur e 19: r andom r ead a c t iming (8-b it m ode) ........................................................................................... 71 f igur e 20: r andom r ead a c t iming (16-b it m ode) ......................................................................................... 71 f igur e 21: by te# t r ansition r ead a c t iming .................................................................................................. 72 f igur e 22: p age r ead a c t iming (16-b it m ode) ............................................................................................... 72 f igur e 23: we#-c ontr olled p r ogr am a c t iming (8-b it m ode) .......................................................................... 74 f igur e 24: we#-c ontr olled p r ogr am a c t iming (16-b it m ode) ......................................................................... 75 f igur e 25: ce#-c ontr olled p r ogr am a c t iming (8-b it m ode) ........................................................................... 77 f igur e 26: ce#-c ontr olled p r ogr am a c t iming (16-b it m ode) ......................................................................... 78 f igur e 27: chip/b lock e r ase a c t iming (8-b it m ode) ...................................................................................... 79 f igur e 28: a cceler ated p r ogr am a c t iming ..................................................................................................... 80 f igur e 29: d ata p olling a c t iming .................................................................................................................. 80 f igur e 30: t oggle/alter nativ e t oggle b it p olling a c t iming (8-b it m ode) .......................................................... 81 f igur e 31: 56-pin t sop C 14mm x 20mm ........................................................................................................ 83 f igur e 32: 48-pin t sop C 12mm x 20mm ........................................................................................................ 84 f igur e 33: 48-b all bga C 6mm x 8mm ............................................................................................................. 85 figure 34: 64-ball fortified bga C 11mm x 13mm ........................................................................................... 86 32mb, 64mb, 128mb: 3v embedded parallel nor flash features pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 6 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. list of t ables t able 1: p ar t n umber i nfor mation ................................................................................................................... 2 t able 2: s tandar d p ar t n umbers b y d ensity , m edium, and p ackage ................................................................... 2 t able 3: p ar t n umbers with s ecur ity f eatur es b y d ensity , m edium, and p ackage ................................................ 3 t able 4: s ignal d escr iptions ........................................................................................................................... 13 t able 5: 32mb m emor y m ap C x8 t op and b ottom b oot [70:0] ......................................................................... 15 t able 6: 32mb m emor y m ap C x16 t op and b ottom b oot [70:0] ........................................................................ 15 t able 7: 32mb m emor y m ap C x8/x16 u nifor m b locks [63:0] ............................................................................ 16 t able 8: 64mb m emor y m ap C x8 t op and b ottom b oot [134:0] ........................................................................ 17 t able 9: 64mb m emor y m ap C x16 t op and b ottom b oot [134:0] ...................................................................... 17 t able 10: 64mb m emor y m ap C x8/x16 u nifor m b locks [127:0] ........................................................................ 18 t able 11: 128mb m emor y m ap C x8/x16 u nifor m b locks [127:0] ...................................................................... 19 t able 12: b us o per ations ............................................................................................................................... 20 t able 13: s tatus r egister b it d efinitions ......................................................................................................... 22 t able 14: o per ations and c orr esponding b it s ettings ...................................................................................... 23 t able 15: lock r egister b it d efinitions ............................................................................................................ 27 t able 16: b lock p r otection s tatus ................................................................................................................... 27 t able 17: s tandar d c ommand d efinitions C a ddr ess-d ata c y cles , 8-b it and 16-b it ........................................... 30 t able 18: r ead e lectr onic s ignatur e ............................................................................................................... 34 t able 19: b lock p r otection ............................................................................................................................. 35 t able 20: b lock p r otection c ommand d efinitions C a ddr ess-d ata c y cles , 8-b it and 16-b it ................................ 47 t able 21: e xtended m emor y b lock a ddr ess and d ata ...................................................................................... 53 t able 22: v pp /wp# f unctions ......................................................................................................................... 55 t able 23: q uer y s tr uctur e ov er view ............................................................................................................... 59 t able 24: cfi q uer y i dentification s tr ing ........................................................................................................ 59 t able 25: cfi q uer y s ystem i nter face i nfor mation .......................................................................................... 60 t able 26: d evice g eometr y d efinition ............................................................................................................ 60 t able 27: e r ase b lock r egion i nfor mation ....................................................................................................... 61 t able 28: p r imar y algor ithm-s pecific e xtended q uer y t able ........................................................................... 62 t able 29: p o w er -u p s pecifications ................................................................................................................. 64 t able 30: r eset a c s pecifications ................................................................................................................... 65 t able 31: a bsolute m aximum/m inimum r atings ............................................................................................ 66 t able 32: o per ating c onditions ...................................................................................................................... 66 t able 33: i nput/o utput c apacitance .............................................................................................................. 67 t able 34: dc c urr ent char acter istics .............................................................................................................. 68 t able 35: dc v oltage char acter istics .............................................................................................................. 69 t able 36: r ead a c char acter istics .................................................................................................................. 70 t able 37: we#-c ontr olled w r ite a c char acter istics ......................................................................................... 73 t able 38: ce#-c ontr olled w r ite a c char acter istics ......................................................................................... 76 t able 39: a cceler ated p r ogr am and d ata p olling/d ata t oggle a c char acter istics .............................................. 80 table 40: program/erase characteristics ........................................................................................................ 82 32mb, 64mb, 128mb: 3v embedded parallel nor flash features pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 7 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. general description the m29e w is an asynchr onous , par allel nor f lash memor y device manufactur ed on 65nm single-bit cell (sbc) technology . read , erase, and pr ogram oper ations ar e per for med using a single lo w-v oltage supply . u pon po w er -up , the device defaults to r ead arr ay mode . the main memor y arr ay is divided into unifor m blocks that can be er ased independent- ly so that v alid data can be pr eser v ed while old data is pur ged. pr ogram and erase commands ar e wr itten to the command inter face of the memor y . an on-chip pr ogr am/ er ase contr oller simplifies the pr ocess of pr ogr amming or er asing the memor y b y taking car e of all special oper ations r equir ed to update the memor y contents . the end of a pr ogram or erase oper ation can be detected and any err or condition can be identi- fied. the command set r equir ed to contr ol the device is consistent with jedec stand- ar ds . ce#, oe#, and we# contr ol the bus oper ation of the device and enable a simple con- nection to most micr opr ocessors , often without additional logic . the m29e w suppor ts asynchr onous r andom r ead and page r ead fr om all blocks of the arr ay . i t also featur es an inter nal pr ogr am buffer that impr o v es thr oughput b y pr ogr am- ming 256 wor ds via one command sequence . the device contains a 128-wor d extended memor y block which o v erlaps addr esses with arr ay block 0. the user can pr ogr am this additional space and then pr otect it to per manently secur e the contents . the device al- so featur es differ ent lev els of har dwar e and softwar e pr otection to secur e blocks fr om unwanted modification. figur e 1: logic diagram v cc v ccq a[max:0] we# v pp /wp# dq[14:0] dq15/a-1 v ss 15 ce# oe# rst# byte# ry/by# 32mb, 64mb, 128mb: 3v embedded parallel nor flash general description pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 8 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. signal assignments figur e 2: 56-pin tsop (t op v iew) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 rfu a22 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# rst# a21 v pp /wp# ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 rfu rfu rfu rfu a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 rfu v ccq notes: 1. a-1 is the least significant address bit in x8 mode. 2. a21 is valid for 64mb and above; otherwise, it is rfu. 3. a22 is valid for 128mb and above; otherwise, it is rfu. 4. rfu = reserved for future use. 32mb, 64mb, 128mb: 3v embedded parallel nor flash signal assignments pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 9 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 3: 48-pin tsop (t op v iew) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# rst# a21 v pp /wp# ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# ce# v ss notes: 1. a-1 is the least significant address bit in x8 mode. 2. a21 is valid for 64mb and above; otherwise, it is rfu. 3. rfu = reserved for future use. 32mb, 64mb, 128mb: 3v embedded parallel nor flash signal assignments pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 10 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 4: 48-ball bga (t op and bottom v iews) a b c d e f g h a b c d e f g h 1 a3 a2 a4 a1 a0 ce# oe# 2 a7 a17 a6 a5 d0 d8 d9 d1 v ss 3 ry/by# v pp /wp# a18 a20 d2 d10 d11 d3 3 ry/by# v pp /wp# a18 a20 d2 d10 d11 d3 4 we# rst# a21 a19 d5 d12 v cc d4 4 we# rst# a21 a19 d5 d12 v cc d4 5 a9 a8 a10 a11 d7 d14 d13 d6 5 a9 a8 a10 a11 d7 d14 d13 d6 6 a13 a12 a14 a15 a16 byte# d15/a-1 v ss 6 a13 a12 a14 a15 a16 byte# d15/a-1 v ss 2 a7 a17 a6 a5 d0 d8 d9 d1 1 a3 a4 a2 a1 a0 ce# oe# v ss bga top view C ball side down bga bottom view C ball side up notes: 1. a-1 is the least significant address bit in x8 mode. 2. a21 is valid for 64mb and above; otherwise, it is rfu. 3. rfu = reserved for future use. 32mb, 64mb, 128mb: 3v embedded parallel nor flash signal assignments pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 11 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 5: 64-ball fortified bga (t op and bottom v iews) a b c d e f g h a b c d e f g h 1 rfu rfu rfu rfu rfu v ccq rfu rfu 2 a3 a4 a2 a1 a0 ce# oe# v ss 3 a7 a17 a6 a5 d0 d8 d9 d1 4 ry/by# v pp /wp# a18 a20 d2 d10 d11 d3 4 ry/by# v pp /wp# a18 a20 d2 d10 d11 d3 5 we# rst# a21 a19 d5 d12 v cc d4 5 we# rst# a21 a19 d5 d12 v cc d4 6 a9 a8 a10 a11 d7 d14 d13 d6 6 a9 a8 a10 a11 d7 d14 d13 d6 7 a13 a12 a14 a15 a16 byte# d15/a-1 v ss 7 a13 a12 a14 a15 a16 byte# d15/a-1 v ss 8 rfu a22 rfu v ccq v ss rfu rfu rfu 8 rfu a22 rfu v ccq v ss rfu rfu rfu 3 a7 a17 a6 a5 d0 d8 d9 d1 2 a3 a4 a2 a1 a0 ce# oe# v ss 1 rfu rfu rfu rfu rfu v ccq rfu rfu fortified bga top view C ball side down fortified bga bottom view C ball side up notes: 1. a-1 is the least significant address bit in x8 mode. 2. a21 is valid for 64mb and above; otherwise, it is rfu. 3. a22 is valid for 128mb and above; otherwise, it is rfu. 4. rfu = reserved for future use. 32mb, 64mb, 128mb: 3v embedded parallel nor flash signal assignments pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 12 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. signal descriptions the signal description table below is a comprehensive list of signals for this device fami- ly. all signals listed may not be supported on this device. see signal assignments for in- formation specific to this device. table 4: signal descriptions name type description a[max:0] input address: selects the cells in the array to access during read operations. during write oper- ations, they control the commands sent to the command interface of the program/erase con- troller. ce# input chip enable: activates the device, enabling read and write operations to be performed. when ce# is high, the device goes to standby and data outputs are at high-z. oe# input output enable: controls the bus read operation. we# input write enable: controls the bus write operation of the command interface. v pp /wp# input v pp /w rite pr otect: provides write protect function and v pph function. these functions protect the lowest or highest block or top two blocks or bottom two blocks, enable the de- vice to enter unlock bypass mode and accelerate program speed, respectively . (refer to hard- ware protection, bypass operations, and program operations for details.) a 0.1 f capacitor should be connected between v pp /wp# and v ss to decouple the current surges from the power supply when v pph is applied. the pcb track widths must be suf ficient to carry the currents required during program and erase operation when v pph is applied (see dc characteristics). byte# input byte/wor d organization select: switches between x8 and x16 bus modes. when byte# is low, the device is in x8 mode; when high, the device is in x16 mode. rst# input reset: applies a hardware reset to the device, which is achieved by holding rst# low for at least t plpx. after rst# goes high, the device is ready for read and write operations (after t phel or t rhel, whichever occurs last). see reset ac specifications for more details. dq[7:0] i/o data i/o: outputs the data stored at the selected address during a read operation. during write operations, they represent the commands sent to the command interface of the inter- nal state machine. dq[14:8] i/o data i/o: outputs the data stored at the selected address during a read operation when byte# is high. when byte# is low, these pins are not used and are high-z. during write operations, these bits are not used. when reading the status register, these bits should be ig- nored. dq15/a-1 i/o data i/o or addr ess input: when the device operates in x16 bus mode, this pin behaves as data i/o, together with dq[14:8]. when the device operates in x8 bus mode, this pin behaves as the least significant bit of the address. except where stated explicitly otherwise, dq15 = data i/o (x16 mode); a-1 = address input (x8 mode). 32mb, 64mb, 128mb: 3v embedded parallel nor flash signal descriptions pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 13 micron t echnology , inc. reserves the right to change products or specifications without notice. 2012 micron technology, inc. all rights reserved. table 4: signal descriptions (continued) name type description ry/by# output ready busy: open-drain output that can be used to identify when the device is performing a program or erase operation. during program or erase operations, r y/by# is low , and is high-z during read mode, auto select mode, and erase suspend mode. after a hard- ware reset, read and write operations cannot begin until r y/by# goes high-z (see reset ac specifications for more details). the use of an open-drain output enables the r y/by# pins from several devices to be connec- ted to a single pull-up resistor to v ccq . a low value will then indicate that one (or more) of the devices is (are) busy. a 10k ohm or bigger resistor is recommended as pull-up resistor to achieve 0.1v v ol . v cc supply supply voltage: provides the power supply for read, program, and erase operations. the command interface is disabled when v cc <= v lko . this prevents write operations from accidentally damaging the data during power -up, power -down, and power surges. if the pro- gram/erase controller is programming or erasing during this time, then the operation aborts and the contents being altered will be invalid. a 0.1 f capacitor should be connected between v cc and v ss to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations (see dc characteristics). v ccq supply i/o supply voltage: provides the power supply to the i/o pins and enables all outputs to be powered independently from v cc . v ss supply ground: all v ss pins must be connected to the system ground. rfu C reserved for future use: rfus should be not connected. memory organization memory configuration the 32mb device memor y arr ay (x8/x16) is divided into 63 main blocks (64kb each) and 8 top or bottom boot blocks (8kb each). i t is also divided into 64 main unifor m blocks (64kb each). the 64mb device memor y arr ay (x8/x16) is divided into 127 main blocks (64kb each) and 8 top or bottom boot blocks (8kb each). i t is also divided into 128 main unifor m blocks (64kb each). the 128mb device memory array (x8/x16) is divided into 128 main uniform blocks (128kb each). 32mb, 64mb, 128mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 14 micron t echnology , inc. reserves the right to change products or specifications without notice. 2012 micron technology, inc. all rights reserved. memory map C 32mb table 5: 32mb memory map C x8 top and bottom boot [70:0] block block size address range (x8 top boot) block block size address range (x8 bottom boot) start end start end 70 8kb 003f e000 003f ffff 70 64kb 003f 0000 003f ffff 69 003f c000 003f dfff 69 003e 0000 003e ffff 68 003f a000 003f bfff 68 003d 0000 003d ffff 67 003f 8000 003f 9fff ? ? ? ? 66 003f 6000 003f 7fff 8 64kb 0001 0000 0001 ffff 65 003f 4000 003f 5fff 7 8kb 0000 e000 0000 ffff 64 003f 2000 003f 3fff 6 0000 c000 0000 dfff 63 003f 0000 003f 1fff 5 0000 a000 0000 bfff 62 64kb 003e 0000 003e ffff 4 0000 8000 0000 9fff ? ? ? ? 3 0000 6000 0000 7fff 2 64kb 0002 0000 0002 ffff 2 0000 4000 0000 5fff 1 0001 0000 0001 ffff 1 0000 2000 0000 3fff 0 0000 0000 0000 ffff 0 0000 0000 0000 1fff table 6: 32mb memory map C x16 top and bottom boot [70:0] block block size address range (x16 top boot) block block size address range (x16 bottom boot) start end start end 70 4kw 001f f000 001f ffff 70 32kw 001f 8000 001f ffff 69 001f e000 001f efff 69 001f 0000 001f 7fff 68 001f d000 001f dfff 68 001e 8000 001e ffff 67 001f c000 001f cfff ? ? ? ? 66 001f b000 001f bfff 8 32kw 0000 8000 0000 ffff 65 001f a000 001f afff 7 4kw 0000 7000 0000 7fff 64 001f 9000 001f 9fff 6 0000 6000 0000 6fff 63 001f 8000 001f 8fff 5 0000 5000 0000 5fff 62 32kw 001f 0000 001f 7fff 4 0000 4000 0000 4fff ? ? ? ? 3 0000 3000 0000 3fff 2 32kw 0001 0000 0001 7fff 2 0000 2000 0000 2fff 1 0000 8000 0000 ffff 1 0000 1000 0000 1fff 0 0000 0000 0000 7fff 0 0000 0000 0000 0fff 32mb, 64mb, 128mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 15 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 7: 32mb memory map C x8/x16 uniform blocks [63:0] block block size address range (x8) block block size address range (x16) start end start end 63 64kb 03f 0000h 03f ffffh 63 32kw 01f 8000h 01f ffffh ? ? ? ? ? ? 0 000 0000h 000 ffffh 0 000 0000h 000 7fffh 32mb, 64mb, 128mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 16 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. memory map C 64mb table 8: 64mb memory map C x8 top and bottom boot [134:0] block block size address range (x8 top boot) block block size address range (x8 bottom boot) start end start end 134 8kb 007f e000 007f ffff 134 64kb 007f 0000 007f ffff 133 007f c000 007f dfff 133 007e 0000 007e ffff 132 007f a000 007f bfff 132 007d 0000 007d ffff 131 007f 8000 007f 9fff ? ? ? ? 130 007f 6000 007f 7fff 8 64kb 0001 0000 0001 ffff 129 007f 4000 007f 5fff 7 8kb 0000 e000 0000 ffff 128 007f 2000 007f 3fff 6 0000 c000 0000 dfff 127 007f 0000 007f 1fff 5 0000 a000 0000 bfff 126 64kb 007e 0000 007e ffff 4 0000 8000 0000 9fff ? ? ? ? 3 0000 6000 0000 7fff 2 64kb 0002 0000 0002 ffff 2 0000 4000 0000 5fff 1 0001 0000 0001 ffff 1 0000 2000 0000 3fff 0 0000 0000 0000 ffff 0 0000 0000 0000 1fff table 9: 64mb memory map C x16 top and bottom boot [134:0] block block size address range (x16 top boot) block block size address range (x16 bottom boot) start end start end 134 4kw 003f f000 003f ffff 134 32kw 003f 8000 003f ffff 133 003f e000 003f efff 133 003f 0000 003f 7fff 132 003f d000 003f dfff 132 003e 8000 003e ffff 131 003f c000 003f cfff ? ? ? ? 130 003f b000 003f bfff 8 32kw 0000 8000 0000 ffff 129 003f a000 003f afff 7 4kw 0000 7000 0000 7fff 128 003f 9000 003f 9fff 6 0000 6000 0000 6fff 127 003f 8000 003f 8fff 5 0000 5000 0000 5fff 126 32kw 003f 0000 003f 7fff 4 0000 4000 0000 4fff ? ? ? ? 3 0000 3000 0000 3fff 2 32kw 0001 0000 0001 7fff 2 0000 2000 0000 2fff 1 0000 8000 0000 ffff 1 0000 1000 0000 1fff 0 0000 0000 0000 7fff 0 0000 0000 0000 0fff 32mb, 64mb, 128mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 17 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 10: 64mb memory map C x8/x16 uniform blocks [127:0] block block size address range (x8) block block size address range (x16) start end start end 127 64kb 07f 0000h 07f ffffh 127 32kw 03f 8000h 03f ffffh ? ? ? ? ? ? 63 03f 0000h 03f ffffh 63 01f 8000h 01f ffffh ? ? ? ? ? ? 0 000 0000h 000 ffffh 0 000 0000h 000 7fffh 32mb, 64mb, 128mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 18 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. memory map C 128mb table 11: 128mb memory map C x8/x16 uniform blocks [127:0] block block size address range (x8) block block size address range (x16) start end start end 127 128kb 0fe 0000h 0ff ffffh 127 64kw 07f 0000h 07f ffffh ? ? ? ? ? ? 63 07e 0000h 07f ffffh 63 03f 0000h 03f ffffh ? ? ? ? ? ? 0 000 0000h 001 ffffh 0 000 0000h 000 ffffh 32mb, 64mb, 128mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 19 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. bus operations t able 12: bus operations notes 1 and 2 apply to entire table operation ce# oe# we# rst# v pp /wp# 8-bit mode 16-bit mode a[max:0], dq15/a-1 dq[14:8] dq[7:0] a[max:0] dq15/a-1, dq[14:0] read l l h h x byte address high-z data output word address data output write l h l h h 3 command address high-z data input 4 command address data input 4 standby h x x h h x high-z high-z x high-z output disable l h h h x x high-z high-z x high-z reset x x x l x x high-z high-z x high-z notes: 1. t ypical glitches of less than 3ns on ce#, we#, and rst# are ignored by the device and do not af fect bus operations. 2. h = logic level high (v ih ); l = logic level low (v il ); x = high or low . 3. if wp# is low , then the highest or the lowest block remains protected, or the top two blocks or the bottom two blocks, depending on line item. 4. data input is required when issuing a command sequence or when performing data polling or block protection. read b us read oper ations r ead fr om the memor y cells , r egisters , or cfi space . t o acceler ate the read oper ation, the memor y arr ay can be r ead in page mode wher e data is inter - nally r ead and stor ed in a page buffer . p age siz e is 8 wor ds (16 b ytes) and is addr essed b y addr ess inputs a[2:0] in x16 bus mode and a[2:0] plus dq15/a-1 in x8 bus mode . the extended memor y blocks and cfi ar ea do not suppor t page r ead mode . a v alid bus read oper ation inv olv es setting the desir ed addr ess on the addr ess inputs , taking ce# and oe# l o w , and holding we# high. the data i/o s will output the v alue . (s ee a c char acter istics for details about when the output becomes v alid.) w rite b us write oper ations wr ite to the command inter face . a v alid bus write oper ation begins b y setting the desir ed addr ess on the addr ess inputs . the addr ess inputs ar e latched b y the command inter face on the falling edge of ce# or we#, whichev er occurs last. the data i/o s ar e latched b y the command inter face on the r ising edge of ce# or we#, whichev er occurs first. oe# must r emain high dur ing the entir e bus write oper - ation. (s ee a c char acter istics for timing r equir ement details .) standby d r iving ce# high in r ead mode causes the device to enter standb y , and data i/o s to be high-z. to reduce the supply current to the standby supply current (i cc2 ), ce# must be held within v cc 0.3v. (see dc characteristics.) 32mb, 64mb, 128mb: 3v embedded parallel nor flash bus operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 20 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. d ur ing pr ogram or erase oper ations the device will continue to use the pr ogr am/ er ase supply curr ent (i c c3 ) until the oper ation completes . output disable d ata i/o s ar e h igh-z when oe# is high. reset d ur ing r eset mode the device is deselected and the outputs ar e h igh-z. the device is in reset mode when rst# is low. the power consumption is reduced to the standby level, independently from ce#, oe#, or we# inputs. 32mb, 64mb, 128mb: 3v embedded parallel nor flash bus operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 21 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. registers status register t able 13: status register bit definitions note 1 applies to entire table bit name settings description notes dq7 data polling bit 0 or 1, depending on operations monitors whether the program/erase controller has successful- ly completed its operation, or has responded to an erase sus- pend operation. 2, 3, 4 dq6 toggle bit toggles: 0 to 1; 1 to 0; and so on monitors whether the program/erase controller has successful- ly completed its operations, or has responded to an erase suspend operation. during a program/erase operation, dq6 toggles from 0 to 1, 1 to 0, and so on, with each succes- sive read operation from any address. 3, 4, 5 dq5 error bit 0 = success 1 = failure identifies errors detected by the program/erase controller . dq5 is set to 1 when a program, block erase, or chip erase op- eration fails to write the correct data to the memory, or when a blank check operation fails. 4, 6 dq3 erase timer bit 0 = erase not in progress 1 = erase in progress identifies the start of program/erase controller operation dur - ing a block erase command. before the program/erase con- troller starts, this bit set to 0, and additional blocks to be erased can be written to the command interface. 4 dq2 alternative toggle bit toggles: 0 to 1; 1 to 0; and so on monitors the program/erase controller during erase opera- tions. during chip erase, block erase, and erase suspend operations, dq2 toggles from 0 to 1, 1 to 0, and so on, with each successive read operation from addresses within the blocks being erased. 3, 4 dq1 buffered program abort bit 1 = abort indicates a buffer program operation abort. the buffered program abort and reset command must be issued to re- turn the device to read mode (see write to buffer pro- gram command). notes: 1. the status register can be read during program, erase, or erase suspend operations; the read operation outputs data on dq[7:0]. 2. for a program operation in progress, dq7 outputs the complement of the bit being programmed. for a read operation from the address previously programmed success- fully , dq7 outputs existing dq7 data. for a read operation from addresses with blocks to be erased while an erase suspend operation is in progress, dq7 outputs 0; upon successful completion of the erase suspend operation, dq7 outputs 1. for an erase or blank check operation in progress, dq7 outputs 0; upon either operation's successful completion, dq7 outputs 1. 3. after successful completion of a program, erase, or blank check operation, the de- vice returns to read mode. 4. during erase suspend mode, read operations to addresses within blocks not being erased output memory array data as if in read mode. a protected block is treated the same as a block not being erased. see the t oggle flowchart for more information. 5. during erase suspend mode, dq6 toggles when addressing a cell within a block being erased. the toggling stops when the program/erase controller has suspended the erase operation. see the toggle flowchart for more information. 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 22 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. 6. when dq5 is set to 1, a read/reset command must be issued before any subsequent command. t able 14: operations and corr esponding bit settings note 1 applies to entire table operation address dq7 dq6 dq5 dq3 dq2 dq1 ry/by# notes program any address dq7# toggle 0 C C 0 0 2 blank check any address 1 toggle 0 C C 0 0 chip erase any address 0 toggle 0 1 toggle C 0 block erase before time-out erasing block 0 toggle 0 0 toggle C 0 non-erasing block 0 toggle 0 0 no toggle C 0 block erase erasing block 0 toggle 0 1 toggle C 0 non-erasing block 0 toggle 0 1 no toggle C 0 program suspend programming block invalid operation high-z nonprogramming block outputs memory array data as if in read mode high-z erase suspend erasing blk 1 no toggle 0 C toggle C high-z non-erasing blk outputs memory array data as if in read mode high-z program during erase suspend erasing block dq7# toggle 0 C toggle C 0 2 non-erasing block dq7# toggle 0 C no toggle C 0 2 buffered program abort any address dq7# toggle 0 C C 1 high-z program error any address dq7# toggle 1 C C C high-z 2 erase error erase success block 0 toggle 1 1 no toggle C high-z erase fail block 0 toggle 1 1 toggle C high-z blank check er- ror any address 1 toggle 1 1 toggle C high-z notes: 1. unspecified data bits should be ignored. 2. dq7# for buffer program is related to the last address location loaded. 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 23 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 6: data polling flowchart start dq7 = data dq5 = 1 dq1 = 1 dq7 = data no no no no yes yes yes yes read dq7, dq5, and dq1 at valid address 1 read dq7 at valid address success failure 2 notes: 1. v alid address is the address being programmed or an address within the block being erased or on which a blank check operation has been executed. 2. the data polling process does not support the blank check operation. the process represented in the t oggle bit flowchart figure can provide information on the blank check operation. 3. failure results: dq5 = 1 indicates an operation error; dq1 = 1 indicates a write to buf- fer program abort operation. 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 24 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 7: t oggle bit flowchart dq6 = toggle dq5 = 1 dq6 = toggle no no yes yes yes start read dq6 at valid address read dq6, dq5, and dq1 at valid address read dq6 (twice) at valid address success failure 1 dq1 = 1 no yes no note: 1. failure results: dq5 = 1 indicates an operation error; dq1 = 1 indicates a write to buf- fer program abort operation. 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 25 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 8: status register polling flowchart write to buffer program start dq7 = valid data dq5 = 1 yes no no yes yes dq6 = toggling yes no no no yes program operation no no dq6 = toggling no dq2 = toggling yes yes yes dq1 = 1 read 3 correct data? no yes read 1 read 2 read 2 read 3 device busy: repolling device busy: repolling read 3 program operation complete program operation failure write to buffer program abort timeout failure erase operation complete erase/suspend mode device error read2.dq6 = read3.dq6 read2.dq2 = read3.dq2 read1.dq6 = read2.dq6 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 26 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. lock register t able 15: lock register bit definitions note 1 applies to entire table bit name settings description notes dq2 password protection mode lock bit 0 = password protection mode enabled 1 = password protection mode disabled (default) places the device permanently in password protection mode. 2 dq1 nonvolatile protection mode lock bit 0 = nonvolatile protection mode enabled with pass- word protection mode permanently disabled 1 = nonvolatile protection mode enabled (default) places the device in nonvolatile protection mode with pass- word protection mode permanently disabled. when shipped from the factory, the device will operate in nonvolatile protec- tion mode, and the memory blocks are unprotected. 2 dq0 extended memory block protection bit 0 = protected 1 = unprotected (default) if the device is shipped with the extended memory block un- locked, the block can be protected by setting this bit to 0. the extended memory block protection status can be read in auto select mode by issuing an auto select command. notes: 1. the lock register is a 16-bit, one-time programmable register . dq[15:3] are reserved and are set to a default value of 1. 2. the password protection mode lock bit and nonvolatile protection mode lock bit cannot both be programmed to 0. any attempt to program one while the other is programmed causes the operation to abort, and the device returns to read mode. the device is ship- ped from the factory with the default setting. table 16: block protection status nonvolatile protection bit lock bit 1 nonvolatile protection bit 2 v olatile protection bit 3 block protection status block protection status 1 1 1 00h block unprotected; nonvolatile protection bit changea- ble. 1 1 0 01h block protected by volatile protection bit; nonvolatile protection bit changeable. 1 0 1 01h block protected by nonvolatile protection bit; nonvola- tile protection bit changeable. 1 0 0 01h block protected by nonvolatile protection bit and vola- tile protection bit; nonvolatile protection bit changea- ble. 0 1 1 00h block unprotected; nonvolatile protection bit un- changeable. 0 1 0 01h block protected by volatile protection bit; nonvolatile protection bit unchangeable. 0 0 1 01h block protected by nonvolatile protection bit; nonvola- tile protection bit unchangeable. 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 27 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 16: block protection status (continued) nonvolatile protection bit lock bit 1 nonvolatile protection bit 2 volatile protection bit 3 block pr otection status block protection status 0 0 0 01h block protected by nonvolatile protection bit and vola- tile protection bit; nonvolatile protection bit unchange- able. notes: 1. nonvolatile protection bit lock bit: when cleared to 1, all nonvolatile protection bits are unlocked; when set to 0, all nonvolatile protection bits are locked. 2. block nonvolatile protection bit: when cleared to 1, the block is unprotected; when set to 0, the block is protected. 3. block volatile protection bit: when cleared to 1, the block is unprotected; when set to 0, the block is protected. figur e 9: lock register pr ogram flowchart start done? dq5 = 1 no no yes yes enter lock register command set address-data (unlock) cycle 1 address-data (unlock) cycle 2 address-data cycle 3 program lock register address-data cycle 1 address-data cycle 2 polling algorithm success: exit protection command set (returns to device read mode) address-data cycle 1 address-data cycle 2 failure: read/reset (returns device to read mode) 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 28 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. notes: 1. each lock register bit can be programmed only once. 2. see the block protection command definitions table for address-data cycle details. 32mb, 64mb, 128mb: 3v embedded parallel nor flash registers pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 29 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. standard command definitions C address-data cycles t able 17: standar d command definitions C addr ess-data cycles, 8-bit and 16-bit note 1 applies to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th 5th 6th a d a d a d a d a d a d read and auto select operations read/reset (f0h) x8 x f0 aaa aa 555 55 x f0 x16 x f0 555 aa 2aa 55 x f0 read cfi (98h) x8 aa 98 x16 55 auto select (90h) x8 aaa aa 555 55 aaa 90 note 2 note 2 2, 3, 4 x16 555 2aa 555 bypass operations unlock bypass (20h) x8 aaa aa 555 55 aaa 20 x16 555 2aa 555 unlock bypass reset (90h/00h) x8 x 90 x 00 x16 program operations program (a0h) x8 aaa aa 555 55 aaa a0 pa pd x16 555 2aa 555 unlock bypass program (a0h) x8 x a0 pa pd 6 x16 double byte/word program (50h) x8 aaa 50 pa2 pd x16 555 quadruple byte/ word program (56h) x8 aaa 56 pa4 pd x16 555 octuple byte pro- gram (8bh) x8 aaa 8b pa8 pd 5 write to buffer program (25h) x8 aaa aa 555 55 bad 25 bad n pa pd 7, 8, 9 x16 555 2aa enhanced write to buffer program (33h) x16 555 aa 2aa 55 bad 33 pa pd 7, 9, 10 unlock bypass write to buffer program (25h) x8 bad 25 bad n pa pd 5 x16 32mb, 64mb, 128mb: 3v embedded parallel nor flash standard command definitions C address-data cycles pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 30 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. t able 17: standar d command definitions C addr ess-data cycles, 8-bit and 16-bit (continued) note 1 applies to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th 5th 6th a d a d a d a d a d a d unlock byp ass enhanced write to buffer program (33h) x16 bad 33 pa pd 10 write to buffer program confirm (29h) x8 bad 29 x16 enhanced write to buffer program confirm (29h) x8 bad 29 x16 buffered program abort and reset (f0h) x8 aaa aa 555 55 aaa f0 x16 555 2aa 555 program suspend (b0h) x8 x b0 x16 program resume (30h) x8 x 30 x16 erase operations chip erase (80/10h) x8 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 x16 555 2aa 555 555 2aa 555 unlock bypass chip erase (80/10h) x8 x 80 x 10 5 x16 block erase (80/30h) x8 aaa aa 555 55 aaa 80 aaa aa 555 55 bad 30 11 x16 555 2aa 555 555 2aa unlock bypass block erase (80/30h) x8 x 80 bad 30 5 x16 erase suspend (b0h) x8 x b0 x16 erase resume (30h) x8 x 30 x16 blank check operations blank check setup (eb/76h) x8 aaa aa 555 55 bad eb bad 76 bad 00 bad 00 x16 555 2aa blank check confirm and read (29h) x8 bad 29 bad note 2 2 x16 notes: 1. a = address; d = data; x = "don't care;" bad = any address in the block; n = number of bytes to be programmed; p a = program address; p a2 = program address with constant amax:a0 for x8 or amax:a1 for x16, which should be used two times to select adjacent 32mb, 64mb, 128mb: 3v embedded parallel nor flash standard command definitions C address-data cycles pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 31 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. two bytes/words; p a4 = program address with constant amax:a1 for x8 or amax:a2 for x16, which should be used four times to select adjacent four bytes/words; p a8 = pro- gram address with constant amax:a2 for x8, which should be used eight times to select adjacent eight bytes; pd = program data; gray shading = not applicable. all values in the table are hexadecimal. some commands require both a command code and sub- code. 2. these cells represent read cycles (versus write cycles for the others). 3. auto select enables the device to read the manufacturer code, device code, block pro- tection status, and extended memory block protection indicator . 4. auto select addresses and data are specified in the electronic signature table and the extended memory block protection table. 5. for any unlock byp ass erase/program command, the first two unlock cycles are unnecessary . 6. this command is only for x8 devices. 7. bad must be the same as the address loaded during the write to buffer program 3rd and 4th cycles. 8. write to buffer program operation: maximum cycles = 261 (x8) and 261 (x16). un- lock byp ass write to buffer program operation: maximum cycles = 259 (x8), 259 (x16). write to buffer program operation: n + 1 = bytes to be programmed; maxi- mum buf fer size = 256 bytes (x8) and 512 bytes (x16). 9. for x8, a[max:7] address pins should remain unchanged while a[6:0] and a-1 pins are used to select a byte within the n + 1 byte page. for x16, a[max:8] address pins should remain unchanged while a[7:0] pins are used to select a word within the n+1 word page. 10. this command is only for x16 devices. for enhanced write to buffer program op- eration, total cycles = 259. for unlock byp ass enhanced write to buffer pro- gram operation, total cycles = 257. 11. block erase address cycles can extend beyond six address-data cycles, depending on the number of blocks to erase. 32mb, 64mb, 128mb: 3v embedded parallel nor flash standard command definitions C address-data cycles pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 32 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. read and auto select operations read/reset command the read/reset (f0h) command r etur ns the device to r ead mode and r esets the err ors in the status r egister . o ne or thr ee bus write oper ations can be used to issue the read/reset command. t o r etur n the device to r ead mode , this command can be issued betw een bus write cy cles befor e the star t of a pr ogram or erase oper ation. i f the read/reset com- mand is issued dur ing the timeout of a bl ock erase oper ation, the device r equir es up to 10 s to abor t, dur ing which time no v alid data can be r ead. this command will not abor t an erase oper ation while in er ase suspend. read cfi command the read cfi (98h) command puts the device in r ead cfi mode and is only v alid when the device is in r ead arr ay or auto select mode . o ne bus write cy cle is r equir ed to issue the command. o nce in r ead cfi mode , bus read oper ations will output data fr om the cfi memor y ar ea (r efer to the c ommon f lash i nter face for details). a read/reset command must be issued to r etur n the device to the pr evious mode (r ead arr ay or auto select ). a sec- ond read/reset command is r equir ed to put the device in r ead arr ay mode fr om auto select mode . auto select command a t po w er -up or after a har dwar e r eset, the device is in r ead mode . i t can then be put in auto select mode b y issuing an a ut o select (90h) command. a uto select mode ena- bles the follo wing device infor mation to be r ead: ? e lectr onic signatur e , which includes manufactur er and device code infor mation as sho wn in the e lectr onic s ignatur e table . ? b lock pr otection, which includes the block pr otection status and extended memor y block pr otection indicator , as sho wn in the b lock p r otection table . e lectr onic signatur e or block pr otection infor mation is r ead b y executing a read oper a- tion with contr ol signals and addr esses set, as sho wn in the r ead e lectr onic s ignatur e table or the b lock p r otection table , r espectiv ely . i n addition, this device infor mation can be r ead or set b y issuing an a ut o select command. a uto select mode can be used b y the pr ogr amming equipment to automatically match a device with the application code to be pr ogr ammed. thr ee consecutiv e bus write oper ations ar e r equir ed to issue an a ut o select com- mand. the device r emains in auto select mode until a read/reset or read cfi com- mand is issued. the device cannot enter auto select mode when a pr ogram or erase oper ation is in progress (ry/by# low). however, auto select mode can be entered if the program or erase operation has been suspended by issuing a program suspend or erase sus- pend command. 32mb, 64mb, 128mb: 3v embedded parallel nor flash read and auto select operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 33 micron t echnology , inc. reserves the right to change products or specifications without notice. 2012 micron technology, inc. all rights reserved. a uto select mode is exited b y per for ming a r eset. the device r etur ns to r ead mode un- less it enter ed auto select mode after an erase susp end or pr ogram susp end command, in which case it returns to erase or program suspend mode. t able 18: read electr onic signatur e note 1 applies to entire table read cycle ce# oe# we# address input data input/output 8-bit/16-bit 8-bit only 8-bit only 16-bit only a[max:11] a[10:4] a3 a2 a1 a0 a-1 dq[14:8] dq[7:0] dq[15:0] manufacturer code l l h x l l l l l x x 89h 0089h device code 1 l l h x l l l l h x x 7eh 227eh device code 2 128mb l l h x l h h h l x x 21h 2221h 64mb boot 10h 2210h 64mb uniform 0ch 220ch 32mb boot 1ah 221ah 32mb uniform 1dh 221dh device code 3 128mb uniform l l h x l h h h h x x 01h 2201h 64mb uniform 64mb top 32mb top device code 3 64mb bottom l l h x l h h h h x x 00h 2200h 32mb bottom 32mb uniform note: 1. h = logic level high (v ih ); l = logic level low (v il ); x = high or low. 32mb, 64mb, 128mb: 3v embedded parallel nor flash read and auto select operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 34 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. t able 19: block pr otection note 1 applies to entire table read cycle ce# oe# we# address input data input/output 8-bit/16-bit 8-bit only 8-bit only 16-bit only a[max:15] a[14:11] a[10:2] a1 a0 a-1 dq[14:8] dq[7:0] dq[15:0] extended memory block protection indicator (dq7) m29ewl 128mb l l h x x l h h x x 89h 2 0089h 2 09h 3 0009h 3 m29ewh 128mb l l h x x l h h x x 99h 2 0099h 2 19h 3 0019h 3 m29ewl 64mb 32mb l l h x x l h h x x 8ah 2 008ah 2 0ah 3 000ah 3 m29ewh 64mb 32mb l l h x x l h h x x 9ah 2 009ah 2 1ah 3 001ah 3 m29ewb 64mb 32mb l l h x x l h h x x 8ah 2 008ah 2 0ah 3 000ah 3 m29ewt 64mb 32mb l l h x x l h h x x 9ah 2 009ah 2 1ah 3 001ah 3 block protection status l l h block base address 6 l l h l x x 01h 4 0001h 4 00h 5 0000h 5 notes: 1. h = logic level high (v ih ); l = logic level low (v il ); x = high or low . 2. micron-prelocked (permanent). 3. customer -lockable. 4. protected: 01h (in x8 mode) is output on dq[7:0]. 5. unprotected: 00h (in x8 mode) is output on dq[7:0]. 6. block base address for 128mb device, should be a[max:16], while a15 = x. bypass operations unlock byp ass command the unl ock byp ass (20h) command is used to place the device in unlock b ypass mode . thr ee bus write oper ations ar e r equir ed to issue the unl ock byp ass com- mand. when the device enters unlock b ypass mode , the two initial unl ock cy cles r equir ed for a standar d pr ogram or erase oper ation ar e not needed, thus enabling faster total pr ogr am or er ase time . the unl ock byp ass command is used in conjunction with unl ock byp ass pr o- gram or unl ock byp ass erase commands to pr ogr am or er ase the device faster than with standard program or erase commands. when the cycle time to the device 32mb, 64mb, 128mb: 3v embedded parallel nor flash bypass operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 35 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. is long, consider able time savings can be gained b y using these commands . when in unlock b ypass mode , only the follo wing commands ar e v alid: ? the unl ock byp ass pr ogram command can be issued to pr ogr am addr esses within the device . ? the unl ock byp ass bl ock erase command can then be issued to er ase one or mor e memor y blocks . ? the unl ock byp ass chip erase command can be issued to er ase the whole mem- or y arr ay . ? the unl ock byp ass write t o b uffer pr ogram and unl ock byp ass en- hanced write t o b uffer pr ogram commands can be issued to speed up the pr ogr amming oper ation. ? the unl ock byp ass reset command can be issued to r etur n the device to r ead mode . i n unlock b ypass mode , the device can be r ead as if in r ead mode . i n addition to the unl ock byp ass command, when v pp /wp# is r aised to v pp h , the de- vice automatically enters unlock b ypass mode . when v pp /wp# r etur ns to v ih or v il , the device is no longer in unlock b ypass mode and nor mal oper ation r esumes . the tr ansi- tions fr om v ih to v pp h and fr om v pp h to v ih must be slo w er than t vhvpp (see the a ccel- er ated p r ogr am, d ata p olling/t oggle a c char acter istics). n ote: m icr on r ecommends the user enter and exit unlock b ypass mode using enter unl ock byp ass and unl ock byp ass reset commands r ather than r aising v pp /wp# to v pp h . v pp /wp# should nev er be r aised to v pp h fr om any mode ex cept r ead mode; oth- er wise , the device may be left in an indeter minate state . unlock byp ass reset command the unl ock byp ass reset (90/00h) command is used to r etur n to r ead/r eset mode fr om unlock b ypass mode . t wo bus write oper ations ar e r equir ed to issue the un- l ock byp ass reset command. the read/reset command does not exit fr om un- lock b ypass mode . pr ogram operations program command the pr ogram (a0h) command can be used to pr ogr am a v alue to one addr ess in the memor y arr ay . the command r equir es four bus write oper ations , and the final write oper ation latches the addr ess and data in the inter nal state machine and star ts the pr o- gr am/er ase contr oller . after pr ogr amming has star ted, bus read oper ations output the status r egister content. p r ogr amming can be suspended and then r esumed b y issuing a pr ogram susp end command and a pr ogram resume command, r espectiv ely . i f the addr ess falls in a pr otected block, the pr ogram command is ignor ed, and the data r emains unchanged. the status r egister is not r ead, and no err or condition is giv en. after the program operation has completed, the device returns to read mode, unless an error has occurred. when an error occurs, bus read operations to the device contin- 32mb, 64mb, 128mb: 3v embedded parallel nor flash program operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 36 micron t echnology , inc. reserves the right to change products or specifications without notice. 2012 micron technology, inc. all rights reserved. ue to output the status r egister . a read/reset command must be issued to r eset the err or condition and r etur n the device to r ead mode . the pr ogram command cannot change a bit set to 0 back to 1, and an attempt to do so is masked dur ing a pr ogram oper ation. i nstead, an erase command must be used to set all bits in one memor y block or in the entir e memor y fr om 0 to 1. the pr ogram oper ation is abor ted b y per for ming a r eset or b y po w er ing-do wn the de- vice . i n this case , data integr ity cannot be ensur ed, and it is r ecommended that the wor ds or b ytes that w er e abor ted be r epr ogr ammed. unlock byp ass program command when the device is in unlock b ypass mode , the unl ock byp ass pr ogram (a0h) command can be used to pr ogr am one addr ess in the memor y arr ay . the command r e- quir es two bus write oper ations instead of four r equir ed b y a standar d pr ogram command; the final write oper ation latches the addr ess and data and star ts the pr o- gr am/er ase contr oller ( the standar d pr ogram command r equir es four bus write op- er ations). the pr ogram oper ation using the unl ock byp ass pr ogram command behav es identically to the pr ogram oper ation using the pr ogram command. the oper ation cannot be abor ted. a bus read oper ation to the memor y outputs the status r egister . double byte/word program command the double by te/w ord pr ogram (50h) command is used to wr ite a page of two adjacent b ytes/wor ds in par allel. the two b ytes/wor ds must differ only for the addr ess a-1 or a0, r espectiv ely . thr ee bus wr ite cy cles ar e necessar y to issue the command: the first bus cy cle sets up the command, the second bus cy cle latches the addr ess and data of the first b yte/wor d to be pr ogr ammed, and the thir d bus cy cle latches the addr ess and data of the second b yte/wor d to be pr ogr ammed and star ts the pr ogr am/er ase con- tr oller . n ote: the double by te/w ord pr ogram command is av ailable only in the 32mb and 64mb devices; also only v ppl is to be applied to the v pp /wp# pin. quadruple byte/word program command the q u adr uple by te/w ord pr ogram (56h) command is used to wr ite a page of four adjacent b ytes/wor ds in par allel. the four b ytes/wor ds must differ for addr esses a0, dq15/a-1 in x8 mode or for addr esses a1, a0 in x16 mode . f iv e bus wr ite cy cles ar e necessar y to issue the command: the first bus cy cle sets up the command, the second bus cy cle latches the addr ess and data of the first b yte/wor d to be pr ogr ammed, the thir d bus cy cle latches the addr ess and data of the second b yte/wor d to be pr ogr am- med, the four th bus cy cle latches the addr ess and data of the thir d b yte/wor d to be pr o- gr ammed, and the fifth bus cy cle latches the addr ess and data of the four th b yte/wor d to be pr ogr ammed and star ts the pr ogr am/er ase contr oller . n ote: the q u adr uple by te/w ord pr ogram command is av ailable only in the 32mb and 64mb devices; also only v ppl is to be applied to the v pp /wp# pin. 32mb, 64mb, 128mb: 3v embedded parallel nor flash program operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 37 micron t echnology , inc. reserves the right to change products or specifications without notice. 2012 micron technology, inc. all rights reserved. octuple byte program command the octuple by te pr ogram (8b h) command is used to wr ite a page of eight adja- cent b ytes in par allel. the eight b ytes must differ for addr esses a1, a0, dq15/a-1 in x8 mode only . n ine bus wr ite cy cles ar e necessar y to issue the command: the first bus cy cle sets up the command, the second bus cy cle latches the addr ess and data of the first b yte to be pr ogr ammed, the thir d bus cy cle latches the addr ess and data of the second b yte to be pr ogr ammed, the four th bus cy cle latches the addr ess and data of the thir d b yte to be pr ogr ammed, the fifth bus cy cle latches the addr ess and data of the four th b yte to be pr ogr ammed, the sixth bus cy cle latches the addr ess and data of the fifth b yte to be pr o- gr ammed, the sev enth bus cy cle latches the addr ess and data of the sixth b yte to be pr o- gr ammed, the eighth bus cy cle latches the addr ess and data of the sev enth b yte to be pr ogr ammed, and the ninth bus cy cle latches the addr ess and data of the eighth b yte to be pr ogr ammed, and star ts the pr ogr am/er ase contr oller . n ote: the octuple by te pr ogram command is av ailable only in the 32mb and 64mb x8 devices; also only v ppl is to be applied to the v pp /wp# pin. write to buffer program command the write t o b uffer pr ogram (25h) command makes use of the pr ogr am buffer to speed up pr ogr amming and dr amatically r educes system pr ogr amming time compar ed to the standar d non-buffer ed pr ogram command. 32mb thr ough 128mb devices sup- por t a 256-wor d maximum pr ogr am buffer . when issuing a write t o b uffer pr ogram command, v pp /wp# can be held high or r aised to v pp h . also , it can be held l o w if the block is not the lo w est or highest block or the top/bottom two blocks , depending on the par t number . when v pp h is applied to the v pp /wp# pin dur ing execution of the command, pr ogr amming speed incr eases (see the a cceler ated p r ogr am, d ata p olling/t oggle a c char acter istics section). the follo wing successiv e steps ar e r equir ed to issue the write t o b uffer pr ogram command: f irst, two unl ock cy cles ar e issued. n ext, a thir d bus write cy cle sets up the write t o b uffer pr ogram command. the set-up code can be addr essed to any location within the tar geted block. then, a four th bus write cy cle sets up the number of wor ds/ b ytes to be pr ogr ammed. v alue n is wr itten to the same block addr ess , wher e n + 1 is the number of wor ds/b ytes to be pr ogr ammed. v alue n + 1 must not ex ceed the siz e of the pr ogr am buffer , or the oper ation will abor t. a fifth cy cle loads the first addr ess and data to be pr ogr ammed. last, n bus write cy cles load the addr ess and data for each wor d/ b yte into the pr ogr am buffer . a ddr esses must lie within the r ange fr om the star t addr ess +1 to the star t addr ess + (n - 1) . o ptimum pr ogr amming per for mance and lo w er po w er usage ar e achiev ed b y aligning the star ting addr ess at the beginning of a 256-wor d boundar y (a[7:0] = 0x000h). any buffer siz e smaller than 256 wor ds is allo w ed within a 256-wor d boundar y , while all ad- dr esses used in the oper ation must lie within the 256-wor d boundar y . i n addition, any cr ossing boundar y buffer pr ogr am will r esult in a pr ogr am abor t. f or a x8 device , maxi- mum buffer size is 256 bytes; for a x16 device, the maximum buffer size is 512 bytes. to program the content of the program buffer, this command must be followed by a write to buffer program confirm command. 32mb, 64mb, 128mb: 3v embedded parallel nor flash program operations pdf: 09005aef84dc44a7 m29ew32mb-128mb.pdf - rev. b 11/12 en 38 micron t echnology , inc. reserves the right to change products or specifications without notice. 2012 micron technology, inc. all rights reserved. i f an addr ess is wr itten sev er al times dur ing a write t o b uffer pr ogram oper ation, the addr ess/data counter will be decr emented at each data load oper ation, and the data will be pr ogr ammed to the last wor d loaded into the buffer . i nv alid addr ess combinations or the incorr ect sequence of bus write cy cles will abor t the write t o b uffer pr ogram command. the status r egister bits dq1, dq5, dq6, dq7 can be used to monitor the device status dur ing a write t o b uffer pr ogram oper ation. the write t o b uffer pr ogram command should not be used to change a bit set to 0 back to 1, and an attempt to do so is masked dur ing the oper ation. r ather than the write t o b uffer pr ogram command, the erase command should be used to set memor y bits fr om 0 to 1. figur e 10: boundary condition of pr ogram buf fer size a n y b u f f e r p r o g r a m a t te m p t i s n o t a l l o w e d 0200h 256-word program buffer is allowed 256-word program buffer is allowed 255 words or less are allowed in the program buffer 0000h 256 words 256 words 0100h 32mb, 64mb, 128mb: 3v embedded parallel nor flash program operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 39 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 11: write to buffer program flowchart abort write to buffer write buffer data, start address start x = n write n, 1 block address write to buffer and program aborted 2 write to a different block address x = 0 write next data, 3 program address pair write to buffer confirm, block address x = x - 1 yes no yes no dq7 = data no yes dq5 = 1 yes no dq1 = 1 no yes write to buffer command, block address read status register (dq1, dq5, dq7) at last loaded address dq7 = data 4 no yes check status register (dq5, dq7) at last loaded address fail or abort 5 end first three cycles of the write to buffer program command notes: 1. n + 1 is the number of addresses to be programmed. 2. the buffered program abor t and reset command must be issued to return the de- vice to read mode. 3. when the block address is specified, any address in the selected block address space is acceptable. however , when loading program buf fer address with data, all addresses must fall within the selected program buf fer page. 4. dq7 must be checked because dq5 and dq7 may change simultaneously . 5. if this flowchart location is reached because dq5 = 1, then the write to buffer pro- gram command failed. if this flowchart location is reached because dq1 = 1, then the write to buffer program command aborted. in both cases, the appropriate reset command must be issued to return the device to read mode: a reset command if the operation failed; a write to buffer program abor t and reset command if the op- eration aborted. 6. see the standard command definitions C address-data cycles, 8-bit and 16-bit table for details about the write to buffer program command sequence. unlock byp ass write to buffer program command when the device is in unlock bypass mode, the unlock bypass write to buffer (25h) command can be used to program the device in fast program mode. the com- 32mb, 64mb, 128mb: 3v embedded parallel nor flash program operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 40 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. mand r equir es two bus write oper ations few er than the standar d write t o b uffer pr ogram command. the unl ock byp ass write t o b uffer pr ogram command behav es the same way as the write t o b uffer pr ogram command: the oper ation cannot be abor ted, and a bus read oper ation to the memor y outputs the status r egister . the write t o b uffer pr ogram c onfirm command is used to confir m an un- l ock byp ass write t o b uffer pr ogram command and to pr ogr am the n + 1 wor ds/b ytes loaded in the pr ogr am buffer b y this command. enhanced write to buffer program command the enhanced write t o b uffer pr ogram (33h) command enables loading 256 wor ds into the wr iter buffer to r educe system pr ogr amming time . each wr ite buffer has the same a[22:8] addr esses . e xecution speed is identical to the 256-wor d write t o b uffer pr ogr am speed (s ee the p r ogr am/e r ase char acter istics table for details). when issuing this command, the v pp /wp# pin can be held high or r aised to v pp h (pr o- gr amming acceler ation). n ote: the enhanced write t o b uffer pr ogram command is av ailable only in the 128mb x16 device , the follo wing successiv e steps ar e r equir ed to issue the command: t wo unlock cy cles begin the command, follo w ed b y a thir d bus wr ite cy cle that sets up the command with setup code that can be addr essed to any location within the tar geted block. the four th bus wr ite cy cle loads the first addr ess and data to be pr ogr ammed. ther e ar e a total of 256 addr ess and data loading cy cles . the command must be follo w ed b y an enhanced write t o b uffer pr ogram c onfirm command to pr ogr am the buffer content, which confir m cy cle ends the command. n ote that addr ess/data cy cles must be loaded in an incr easing addr ess or der (a[7:0] fr om 00h to ffh) that includes all 256 wor ds . i nv alid addr ess combinations or the cor - r ect sequence of bus wr ite cy cles will r esult in an abor t. s tatus r egister bits dq1, dq5, dq6, and dq7 enable monitor ing the device status dur - ing oper ation. a 12v exter nal supply can be used to impr o v e pr ogr amming efficiency . the enhanced write t o b uffer pr ogram command should not be used to change a bit set to 0 back to 1. any attempt to do so is masked dur ing the oper ation. the erase command should be used to set memor y bits fr om 0 to 1. unlock byp ass enhanced write to buffer program command the unl ock byp ass enhanced write t o b uffer pr ogram (33h)command can be used to pr ogr am the memor y in fast pr ogr am mode . the command r equir es two ad- dr ess/data loading cy cles less than the r egular enhanced write t o b uffer pr o- gram command. this command behav es identically to the enhanced write t o b uffer pr ogram command. the oper ation cannot be abor ted and a bus r ead oper a- tion to the memor y outputs the status r egister . this command is confir med b y the en- hanced write to buffer program confirm command, which programs the 256 words loaded in the buffer. 32mb, 64mb, 128mb: 3v embedded parallel nor flash program operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 41 micron t echnology , inc. reserves the right to change products or specifications without notice. 2012 micron technology, inc. all rights reserved. write to buffer program confirm command the write t o b uffer pr ogram c onfirm (29h) command is used to confir m a write t o b uffer pr ogram command and to pr ogr am the n + 1 wor ds/b ytes loaded in the pr ogr am buffer b y this command. enhanced write to buffer program confirm command the enhanced write t o b uffer pr ogram c onfirm (29h) command is used to confir m an enhanced write t o b uffer pr ogram command and to pr ogr am the 256 wor ds loaded in the buffer . buffered program abor t and reset command a b uffered pr ogram abor t and reset (f0h) command must be issued to r eset the device to r ead mode when the b uffer pr ogram oper ation is abor ted. the buffer pr ogr amming sequence can be abor ted in the follo wing ways: ? load a v alue that is gr eater than the page buffer siz e dur ing the number of locations to pr ogr am in the write t o b uffer pr ogram command. ? w r ite to an addr ess in a differ ent block than the one specified dur ing the write b uf- fer l o ad command. ? w r ite an addr ess/data pair to a differ ent wr ite buffer page than the one selected b y the star ting addr ess dur ing the pr ogr am buffer data loading stage of the oper ation. ? w r ite data other than the c onfirm command after the specified number of data load cy cles . the abor t condition is indicated b y dq1 = 1, dq7 = dq7# (for the last addr ess location loaded), dq6 = toggle , and dq5 = 0 (all of which ar e status r egister bits). a b uffered pr ogram abor t and reset command sequence must be wr itten to r eset the device for the next oper ation. n ote: the full thr ee-cy cle b uffered pr ogram abor t and reset command se- quence is r equir ed when using buffer pr ogr amming featur es in unlock b ypass mode . program suspend command the pr ogram susp end (b0h) command can be used to interr upt a pr ogr am oper a- tion so that data can be r ead fr om any block. when the pr ogram susp end command is issued dur ing a pr ogr am oper ation, the device suspends the oper ation within the pr o- gr am suspend latency time and updates the status r egister bits . after the pr ogr am oper ation has been suspended, data can be r ead fr om any addr ess . h o w ev er , data is inv alid when r ead fr om an addr ess wher e a pr ogr am oper ation has been suspended. the pr ogram susp end command may also be issued dur ing a pr ogram oper ation while an er ase is suspended. i n this case , data may be r ead fr om any addr ess not in er ase suspend or pr ogr am suspend mode . t o r ead fr om the extended memor y block ar ea (one-time pr ogr ammable ar ea), the enter/exit extended memor y bl ock command sequences must be issued. the system may also issue the auto select command sequence when the device is in program suspend mode. the system can read as many auto select codes as required. 32mb, 64mb, 128mb: 3v embedded parallel nor flash program operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 42 micron t echnology , inc. reserves the right to change products or specifications without notice. 2012 micron technology, inc. all rights reserved. when the device exits auto select mode , the device r ev er ts to pr ogr am suspend mode and is r eady for another v alid oper ation. the pr ogram susp end oper ation is abor ted b y per for ming a device r eset or po w er - do wn. i n this case , data integr ity cannot be ensur ed, and it is r ecommended that the wor ds or b ytes that w er e abor ted be r epr ogr ammed. program resume command the pr ogram resume (30h) command must be issued to exit a pr ogr am suspend mode and r esume a pr ogram oper ation. the contr oller can use dq7 or dq6 status bits to deter mine the status of the pr ogram oper ation. after a pr ogram resume command is issued, subsequent pr ogram resume commands ar e ignor ed. another pr ogram susp end command can be issued after the device has r esumed pr ogr am- ming. erase operations chip erase command the chip erase (80/10h) command er ases the entir e chip . s ix bus write oper ations ar e r equir ed to issue the command and star t the pr ogr am/er ase contr oller . p r otected blocks ar e not er ased. i f all blocks ar e pr otected, the chip erase oper ation appears to star t, but will ter minate within appr o ximately100 s , leaving the data un- changed. n o err or is r epor ted when pr otected blocks ar e not er ased. d ur ing the chip erase oper ation, the device ignor es all other commands , including erase susp end . i t is not possible to abor t the oper ation. all bus read oper ations dur - ing chip erase output the status r egister on the data i/o s . s ee the s tatus r egister sec- tion for mor e details . after the chip erase oper ation completes , the device r etur ns to r ead mode , unless an err or has occurr ed. i f an err or occurs , the device will continue to output the status r egis- ter . a read/reset command must be issued to r eset the err or condition and r etur n to r ead mode . the chip erase command sets all of the bits in unpr otected blocks of the device to 1. all pr evious data is lost. the oper ation is abor ted b y per for ming a r eset or b y po w er ing-do wn the device . i n this case , data integr ity cannot be ensur ed, and it is r ecommended that the entir e chip be er ased again. unlock byp ass chip erase command when the device is in unlock b ypass mode , the unl ock byp ass chip erase (80/10h) command can be used to er ase all memor y blocks at one time . the command r equir es only two bus write oper ations instead of six using the standar d chip erase com- mand. the final bus write oper ation star ts the pr ogr am/er ase contr oller . the unl ock byp ass chip erase command behav es the same way as the chip erase command: the operation cannot be aborted, and a bus read operation to the memory outputs the status register. 32mb, 64mb, 128mb: 3v embedded parallel nor flash erase operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 43 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. block erase command the bl ock erase (80/30h) command er ases a list of one or mor e blocks . i t sets all of the bits in the unpr otected selected blocks to 1. all pr evious data in the selected blocks is lost. s ix bus write oper ations ar e r equir ed to select the first block in the list. each addition- al block in the list can be selected b y r epeating the sixth bus write oper ation using the addr ess of the additional block. after the command sequence is wr itten, a block er ase timeout occurs . d ur ing the timeout per iod, additional block addr esses and bl ock erase commands can be wr itten. after the pr ogr am/er ase contr oller has star ted, it is not possible to select any mor e blocks . each additional block must ther efor e be selected within the timeout per iod of the last block. the timeout timer r estar ts when an addi- tional block is selected. after the sixth bus write oper ation, a bus read oper ation out- puts the status r egister . s ee the we#-c ontr olled p r ogr am wav efor ms for details on ho w to identify if the pr ogr am/er ase contr oller has star ted the bl ock erase oper ation. after the bl ock erase oper ation completes , the device r etur ns to r ead mode , unless an err or has occurr ed. i f an err or occurs , bus read oper ations will continue to output the status r egister . a read/reset command must be issued to r eset the err or condi- tion and r etur n to r ead mode . i f any selected blocks ar e pr otected, they ar e ignor ed, and all the other selected blocks ar e er ased. i f all of the selected blocks ar e pr otected, the bl ock erase oper ation ap- pears to star t, but will ter minate within appr o ximately100 s , leaving the data un- changed. n o err or condition is giv en when pr otected blocks ar e not er ased. d ur ing the bl ock erase oper ation, the device ignor es all commands ex cept the erase susp end command and the read/reset command, which is accepted only dur ing the timeout per iod. the oper ation is abor ted b y per for ming a r eset or po w er ing- do wn the device . i n this case , data integr ity cannot be ensur ed, and it is r ecommended that the abor ted blocks be er ased again. unlock byp ass block erase command when the device is in unlock b ypass mode , the unl ock byp ass bl ock erase (80/30h) command can be used to er ase one or mor e memor y blocks at a time . the command r equir es two bus write oper ations instead of six using the standar d bl ock erase command. the final bus write oper ation latches the addr ess of the block and star ts the pr ogr am/er ase contr oller . t o er ase multiple blocks (after the first two bus write oper ations hav e selected the first block in the list), each additional block in the list can be selected b y r epeating the sec- ond bus write oper ation using the addr ess of the additional block. the unl ock byp ass bl ock erase command behav es the same way as the bl ock erase command: the oper ation cannot be abor ted, and a bus read oper ation to the memor y outputs the status r egister . s ee the bl ock erase c ommand section for de- tails . erase suspend command the erase susp end (b0h) command tempor ar ily suspends a bl ock erase oper a- tion. one bus write operation is required to issue the command. the block address is "don't care." 32mb, 64mb, 128mb: 3v embedded parallel nor flash erase operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 44 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. the pr ogr am/er ase contr oller suspends the erase oper ation within the er ase suspend latency time of the erase susp end command being issued. h o w ev er , when the erase susp end command is wr itten dur ing the block er ase timeout, the device im- mediately ter minates the timeout per iod and suspends the erase oper ation. after the pr ogr am/er ase contr oller has stopped, the device oper ates in r ead mode , and the er ase is suspended. d ur ing an erase susp end oper ation, it is possible to r ead and execute pr ogram op- er ations or write t o b uffer pr ogram oper ations in blocks that ar e not suspended. b oth read and pr ogram oper ations behav e nor mally on these blocks . r eading fr om blocks that ar e suspended will output the status r egister . i f any attempt is made to pr o- gr am in a pr otected block or in the suspended block, the pr ogram command is ignor - ed, and the data r emains unchanged. i n this case , the status r egister is not r ead, and no err or condition is giv en. i t is also possible to issue a ut o select , read cfi, and unl ock byp ass commands dur ing an erase susp end oper ation. the read/reset command must be issued to r etur n the device to r ead arr ay mode befor e the resume command will be accepted. d ur ing an erase susp end oper ation, a bus read oper ation to the extended memor y block will output the extended memor y block data. after the device enters extended memor y block mode , the exit extended memor y bl ock command must be issued befor e the erase oper ation can be r esumed. an erase susp end command is ignor ed if it is wr itten dur ing a chip erase oper a- tion. i f the erase susp end oper ation is abor ted b y per for ming a device r eset or po w er - do wn, data integr ity cannot be ensur ed, and it is r ecommended that the suspended blocks be er ased again. erase resume command the erase resume (30h) command r estar ts the pr ogr am/er ase contr oller after an erase susp end oper ation. the device must be in r ead arr ay mode befor e the resume command will be accepted. an er ase can be suspended and r esumed mor e than once . blank check operation blank check commands t wo commands ar e r equir ed to execute a bl ank check oper ation: bl ank check setup (eb/76h) and bl ank check c onfirm and read (29h). the bl ank check oper ation deter mines whether a specified block is blank (that is , completely er ased). i t can also be used to deter mine whether a pr evious erase oper a- tion was successful, including erase oper ations that might hav e been interr upted b y po w er loss . the blank check operation checks for cells that are programmed or over-erased. if it finds any, it returns a failure status, indicating that the block is not blank. if it returns a passing status, the block is guaranteed blank (all 1s) and is ready to program. 32mb, 64mb, 128mb: 3v embedded parallel nor flash blank check operation pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 45 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. b efor e executing, the erase oper ation initiates a bl ank check oper ation, and if the tar get block is blank, the erase oper ation is skipped, benefitting o v er all cy cle per for m- ance; other wise , the erase oper ation continues . the bl ank check oper ation can occur in only one block at a time , and dur ing its exe- cution, r eading the status r egister is the only other oper ation allo w ed. r eading fr om any addr ess in the device enables r eading the status r egister to monitor blank check pr o- gr ess or err ors . o per ations such as read (arr ay data), pr ogram, erase, and any sus- pended oper ation ar e not allo w ed. after the bl ank check oper ation has completed, the device r etur ns to r ead mode un- less an err or has occurr ed. when an err or occurs , the device continues to output status register data. a read/reset command must be issued to reset the error condition and return the device to read mode. 32mb, 64mb, 128mb: 3v embedded parallel nor flash blank check operation pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 46 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. block protection command definitions C address-data cycles t able 20: block pr otection command definitions C addr ess-data cycles, 8-bit and 16-bit notes 1 and 2 apply to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th n th a d a d a d a d a d lock register commands enter lock register command set (40h) x8 aaa aa 555 55 aaa 40 3 x16 555 aa 2aa 55 555 program lock register (a0h) x8 x a0 x data 5 x16 read lock register x8 x data 4, 5, 6 x16 password protection commands enter password protection command set (60h) x8 aaa aa 555 55 aaa 60 3 x16 555 aa 2aa 55 555 program password (a0h) x8 x a0 pwan pwdn 7 x16 read password x8 00 pwd0 01 pwd1 02 pwd2 03 pwd3 07 pwd7 4, 6, 8, 9 x16 00 pwd0 01 pwd1 02 pwd2 03 pwd3 unlock password (25h/ 03h) x8 00 25 00 03 00 pwd0 01 pwd1 00 29 8, 10 x16 nonvolatile protection commands enter nonvolatile protection command set (c0h) x8 aaa aa 555 55 aaa c0 3 x16 555 aa 2aa 55 555 program nonvolatile protection bit (a0h) x8 x a0 bad 00 11 x16 read nonvolatile protection bit status x8 bad read(0) 4, 6, 11 x16 clear all nonvolatile protection bits (80/30h) x8 x 80 00 30 12 x16 nonvolatile protection bit lock bit commands enter nonvolatile protection bit lock bit command set (50h) x8 aaa aa 555 55 aaa 50 3 x16 555 aa 2aa 55 555 program nonvolatile protection bit lock bit (a0h) x8 x a0 x 00 11 x16 32mb, 64mb, 128mb: 3v embedded parallel nor flash block protection command definitions C address-data cycles pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 47 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. t able 20: block pr otection command definitions C addr ess-data cycles, 8-bit and 16-bit (continued) notes 1 and 2 apply to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th n th a d a d a d a d a d read nonvola tile protection bit lock bit status x8 x read(0) 4, 6, 11 x16 volatile protection commands enter vola tile protection command set (e0h) x8 aaa aa 555 55 aaa e0 3 x16 555 aa 2aa 55 555 program vola tile protection bit (a0h) x8 x a0 bad 00 11 x16 read vola tile protection bit status x8 bad read(0) 4, 6 x16 clear vola tile protection bit (a0h) x8 x a0 bad 01 11 x16 extended memory block commands enter extended memory block (88h) x8 aaa aa 555 55 aaa 88 3 x16 555 aa 2aa 55 555 exit extended memory block (90/00h) x8 aaa aa 555 55 aaa 90 x 00 x16 555 aa 2aa 55 555 exit protection commands exit protection command set (90/00h) x8 x 90 x 00 3 x16 notes: 1. key: a = address and d = data; x = "dont care;" bad = any address in the block; pwdn = password bytes 0 to 7; pw an = password address, n = 0 to 7; gray = not applicable. all values in the table are hexadecimal. 2. dq[15:8] are "dont care" during unlock and command cycles. a[max:16] are "dont care" during unlock and command cycles, unless an address is required. 3. the enter command sequence must be issued prior to any operation. it disables read and write operations from and to block 0. read and write operations from and to any other block are allowed. also, when an enter command set command is issued, an exit protection command set command must be issued to return the device to read mode. 4. read register/p assword commands have no command code; ce# and oe# are driven low and data is read according to a specified address. 5. data = lock register content. 6. all address cycles shown for this command are read cycles. 7. only one portion of the password can be programmed or read by each program p ass- word command. 8. each portion of the password can be entered or read in any order as long as the entire 64-bit password is entered or read. 32mb, 64mb, 128mb: 3v embedded parallel nor flash block protection command definitions C address-data cycles pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 48 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. 9. for the x8 read p assword command, the n th (and final) address cycle equals the 8th address cycle. from the 5th to the 8th address cycle, the values for each address and da- ta pair continue the pattern shown in the table as follows: for x8, address and data = 04 and pwd4; 05 and pwd5; 06 and pwd6; 07 and pwd7. 10. for the x8 unlock p assword command, the n th (and final) address cycle equals the 11th address cycle. from the 5th to the 10th address cycle, the values for each address and data pair continue the pattern shown in the table as follows: address and data = 02 and pwd2; 03 and pwd3; 04 and pwd4; 05 and pwd5; 06 and pwd6; 07 and pwd7. for the x16 unlock p assword command, the n th (and final) address cycle equals the 7th address cycle. for the 5th and 6th address cycles, the values for the address and data pair continue the pattern shown in the table as follows: address and data = 02 and pwd2; 03 and pwd3. 11. both nonvolatile and volatile protection bit settings are as follows: protected state = 00; unprotected state= 01. 12. the clear all nonvolatile protection bits command programs all nonvolatile pro- tection bits before erasure. this prevents over-erasure of previously cleared nonvolatile protection bits. 32mb, 64mb, 128mb: 3v embedded parallel nor flash block protection command definitions C address-data cycles pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 49 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. pr otection operations b locks can be pr otected individually against accidental pr ogram, erase, or read op- er ations on both 8-bit and 16-bit configur ations . the block pr otection scheme is sho wn in the s oftwar e p r otection scheme figur e . m emor y block and extended memor y block pr otection is configur ed thr ough the lock r egister (see lock r egister section). lock register commands after the enter l ock register c ommand set (40h) command has been issued, all bus read or pr ogram oper ations can be issued to the lock r egister . the pr ogram l ock register (a0h) command allo ws the lock r egister to be config- ur ed. the pr ogr ammed data can then be checked with a read l ock register com- mand b y dr iving ce# and oe# l o w with the appr opr iate addr ess data on the addr ess bus . p assword protection commands after the enter p assw ord pr o tection c ommand set (60h) command has been issued, the commands r elated to passwor d pr otection mode can be issued to the device . the pr ogram p assw ord (a0h) command is used to pr ogr am the 64-bit passwor d used in the passwor d pr otection mode . t o pr ogr am the 64-bit passwor d, the complete command sequence must be enter ed eight times at eight consecutiv e addr esses selec- ted b y a[1:0] plus dq15/a-1 in 8-bit mode , or four times at four consecutiv e addr esses selected b y a[1:0] in 16-bit mode . b y default, all passwor d bits ar e set to 1. the passwor d can be checked b y issuing a read p assw ord command. the read p assw ord command is used to v er ify the passwor d used in passwor d pr o- tection mode . t o v er ify the 64-bit passwor d, the complete command sequence must be enter ed eight times at eight consecutiv e addr esses selected b y a[1:0] plus dq15/a-1 in 8-bit mode , or four times at four consecutiv e addr esses selected b y a[1:0] in 16-bit mode . i f the passwor d mode lock bit is pr ogr ammed and the user attempts to r ead the passwor d, the device will output ffh onto the i/o data bus . the unl ock p assw ord (25/03h) command is used to clear the nonv olatile pr otec- tion bit lock bit, allo wing the nonv olatile pr otection bits to be modified. the unl ock p assw ord command must be issued, along with the corr ect passwor d, and r equir es a 1 s delay betw een successiv e unl ock p assw ord commands in or der to pr ev ent hackers fr om cr acking the passwor d b y tr ying all possible 64-bit combinations . i f this delay does not occur , the latest command will be ignor ed. a ppr o ximately 1 s is r equir ed for unlocking the device after the v alid 64-bit passwor d has been pr o vided. nonvola tile protection commands after the enter nonv ol a tile pr o tection c ommand set (c0h) command has been issued, the commands r elated to nonv olatile pr otection mode can be issued to the device . a block can be pr otected fr om pr ogr am or er ase b y issuing a pr ogram nonv ol a tile protection bit (a0h) command, along with the block address. this command sets the nonvolatile protection bit to 0 for a given block. 32mb, 64mb, 128mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 50 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. the status of a nonv olatile pr otection bit for a giv en block or gr oup of blocks can be r ead b y issuing a read nonv ol a tile modify pr o tection bit command, along with the block addr ess . the nonv olatile pr otection bits ar e er ased simultaneously b y issuing a clear all nonv ol a tile pr o tection bit s (80/30h) command. n o specific block addr ess is r e- quired. if the nonvolatile protection bit lock bit is set to 0, the command fails. 32mb, 64mb, 128mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 51 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 12: pr ogram/erase nonvolatile pr otection bit algorithm no no yes yes dq6 = toggle enter nonvolatile protection command set start program nonvolatile protection bit addr = bad fail read byte twice addr = bad read byte twice addr = bad no no yes yes dq6 = toggle reset dq5 = 1 exit protection command set dq0 = 1 (erase) 0 (program) read byte twice addr = bad wait 500s pass 32mb, 64mb, 128mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 52 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. nonvola tile protection bit lock bit commands after the enter nonv ol a tile pr o tection bit l ock bit c ommand set (50h) command has been issued, the commands that allo w the nonv olatile pr otection bit lock bit to be set can be issued to the device . the pr ogram nonv ol a tile pr o tection bit l ock bit (a0h) command is used to set the nonv olatile pr otection bit lock bit to 0, thus locking the nonv olatile pr otection bits and pr ev enting them fr om being modified. the read nonv ol a tile pr o tection bit l ock bit st a tus command is used to r ead the status of the nonv olatile pr otection bit lock bit. vola tile protection commands after the enter v ol a tile pr o tection c ommand set (e0h) command has been issued, commands r elated to the v olatile pr otection mode can be issued to the device . the pr ogram v ol a tile pr o tection bit (a0h) command individually sets a v ola- tile pr otection bit to 0 for a giv en block. i f the nonv olatile pr otection bit for the same block is set, the block is locked r egar dless of the v alue of the v olatile pr otection bit. (s ee the b lock p r otection s tatus table .) the status of a v olatile pr otection bit for a giv en block can be r ead b y issuing a read v ol a tile pr o tection bit st a tus command along with the block addr ess . the clear v ol a tile pr o tection bit (a0h) command individually clears (sets to 1) the v olatile pr otection bit for a giv en block. i f the nonv olatile pr otection bit for the same block is set, the block is locked r egar dless of the v alue of the v olatile pr otection bit. (s ee the b lock p r otection s tatus table .) extended memor y block commands the device has one extr a 128-wor d extended memor y block that can be accessed only b y the enter extended memor y bl ock (88h) command. the extended memor y block is 128 wor ds (x16) or 256 b ytes (x8). i t is used as a secur ity block to pr o vide a per - manent 128-bit secur ity identification number or to stor e additional infor mation. the device can be shipped with the extended memor y block pr elocked per manently b y m i- cr on, including the 128-bit secur ity identification number . or , the device can be ship- ped with the extended memor y block unlocked, enabling customers to per manently program and lock it. (see lock register, the auto select command, and the block protection table.) table 21: extended memory block address and data address data x8 x16 micron prelocked customer lockable 000000hC00000fh 000000hC000007h secure id number determined by customer secure id number 000010hC0000ffh 000008hC00007fh protected and unavailable determined by customer after the enter extended memor y bl ock command has been issued, the device enters the extended memory block mode. all bus read or program operations are conducted on the extended memory block, and the extended memory block is ad- 32mb, 64mb, 128mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 53 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. dr essed using the addr esses occupied b y block 0 in the other oper ating modes (see the m emor y m ap table). i n extended memor y block mode , erase, chip erase, erase susp end , and erase resume commands ar e not allo w ed. the extended memor y block cannot be er ased, and each bit of the extended memor y block can only be pr ogr ammed once . the extended memor y block is pr otected fr om fur ther modification b y pr ogr amming lock r egister bit 0. o nce inv oked, this pr otection cannot be undone . the device r emains in extended memor y block mode until the exit extended mem- or y bl ock (90/00h) command is issued, which r etur ns the device to r ead mode , or until po w er is r emo v ed fr om the device . after a po w er -up sequence or har dwar e r eset, the device will r ev er t to r eading memor y blocks in the main arr ay . exit protection command the exit pr o tection c ommand set (90/00h) command is used to exit the lock r egister , passwor d pr otection, nonv olatile pr otection, v olatile pr otection, and nonv ola- tile protection bit lock bit command set modes and return the device to read mode. 32mb, 64mb, 128mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 54 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. device pr otection har dwar e pr otection the v pp /wp# function pr o vides a har dwar e method of pr otecting either the highest/ lo w est block or the top/bottom two blocks . when v pp /wp# is l o w , pr ogram and erase oper ations on either of these block options is ignor ed to pr o vide pr otection. when v pp /wp# is high, the device r ev er ts to the pr evious pr otection status for the highest/lo w est block or top/bottom two blocks . pr ogram and erase oper ations can modify the data in either of these block options unless block pr otection is enabled. n ote: m icr on highly r ecommends dr iving v pp /wp# high or l o w . i f a system needs to float the v pp /wp# pin, without a pull-up/pull-down resistor and no capacitor, then an internal pull-up resistor is enabled. table 22: v pp /wp# functions v pp /wp# settings function v il highest/lowest block or the top/bottom two blocks are protected. v ih highest/lowest block or the top/bottom two blocks are unprotected unless software pro- tection is activated. softwar e pr otection f our softwar e pr otection modes ar e av ailable: ? v olatile pr otection ? n onv olatile pr otection ? p asswor d pr otection ? p asswor d access the device is shipped with all blocks unpr otected. o n first use , the device defaults to the nonv olatile pr otection mode but can be activ ated in either the nonv olatile pr otec- tion or passwor d pr otection mode . the desir ed pr otection mode is activ ated b y setting either the nonv olatile pr otection mode lock bit or the passwor d pr otection mode lock bit of the lock r egister (see the lock r egister section). b oth bits ar e one-time-pr ogr ammable and nonv olatile; ther efor e , af- ter the pr otection mode has been activ ated, it cannot be changed, and the device is set per manently to oper ate in the selected pr otection mode . i t is r ecommended that the desir ed softwar e pr otection mode be activ ated when first pr ogr amming the device . f or the lo w est and highest blocks or for the top/bottom two blocks , a higher lev el of block pr otection can be achiev ed b y locking the blocks using nonv olatile pr otection mode and holding v pp /wp# l o w . b locks with v olatile pr otection and nonv olatile pr otection can coexist within the memo- r y arr ay . i f the user attempts to pr ogr am or er ase a pr otected block, the device ignor es the command and r etur ns to r ead mode . the block protection status can be read by performing a read electronic signature or by issuing an auto select command (see the block protection table). 32mb, 64mb, 128mb: 3v embedded parallel nor flash device protection pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 55 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. r efer to the b lock p r otection s tatus table and the s oftwar e p r otection scheme figur e for details on the block pr otection scheme . r efer to the p r otection o per ations section for a descr iption of the command sets . v olatile pr otection mode v olatile pr otection enables the softwar e application to pr otect blocks against inadv er - tent change and can be disabled when changes ar e needed. v olatile pr otection bits ar e unique for each block and can be individually modified. v olatile pr otection bits contr ol the pr otection scheme only for unpr otected blocks whose nonv olatile pr otection bits ar e clear ed to 1. i ssuing a pr ogram v ol a tile pr o tection bit or clear v ol a tile pr o tection bit command sets to 0 or clears to 1 the v olatile pr otection bits and pla- ces the associated blocks in the pr otected (0) or unpr otected (1) state , r espectiv ely . the v olatile pr otection bit can be set or clear ed as often as needed. when the device is first shipped, or after a po w er -up or har dwar e r eset, the v olatile pr o- tection bits default to 1 (unpr otected). nonvolatile pr otection mode a nonv olatile pr otection bit is assigned to each block. each of these bits can be set for pr otection individually b y issuing a pr ogram nonv ol a tile pr o tection bit com- mand. also , each device has one global v olatile bit called the nonv olatile pr otection bit lock bit; it can be set to pr otect all nonv olatile pr otection bits at once . this global bit must be set to 0 only after all nonv olatile pr otection bits ar e configur ed to the desir ed settings . when set to 0, the nonv olatile pr otection bit lock bit pr ev ents changes to the state of the nonv olatile pr otection bits . when clear ed to 1, the nonv olatile pr otection bits can be set and clear ed using the pr ogram nonv ol a tile pr o tection bit and clear all nonv ol a tile pr o tection bit s commands , r espectiv ely . n o softwar e command unlocks the nonv olatile pr otection bit lock bit unless the device is in passwor d pr otection mode; in nonv olatile pr otection mode , the nonv olatile pr otec- tion bit lock bit can be clear ed only b y taking the device thr ough a har dwar e r eset or po w er -up . n onv olatile pr otection bits cannot be clear ed individually ; they must be clear ed all at once using a clear all nonv ol a tile pr o tection bit s command. they will r e- main set thr ough a har dwar e r eset or a po w er -do wn/po w er -up sequence . i f one of the nonv olatile pr otection bits needs to be clear ed (unpr otected), additional steps ar e r equir ed: f irst, the nonv olatile pr otection bit lock bit must be clear ed to 1, us- ing either a po w er -cy cle or har dwar e r eset. then, the nonv olatile pr otection bits can be changed to r eflect the desir ed settings . f inally , the nonv olatile pr otection bit lock bit must be set to 0 to lock the nonv olatile pr otection bits . the device no w will oper ate nor - mally . t o achiev e the best pr otection, the pr ogram nonv ol a tile pr o tection l ock bit command should be executed early in the boot code , and the boot code should be pr o- tected b y holding v pp /wp# l o w . nonvolatile protection bits and volatile protection bits have the same function when v pp /wp# is high or when v pp /wp# is at the voltage for program acceleration (v pph ). 32mb, 64mb, 128mb: 3v embedded parallel nor flash device protection pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 56 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. passwor d pr otection mode the passwor d pr otection mode pr o vides a higher lev el of secur ity than the nonv olatile pr otection mode b y r equir ing a 64-bit passwor d to unlock the nonv olatile pr otection bit lock bit. i n addition to this passwor d r equir ement, the nonv olatile pr otection bit lock bit is set to 0 after po w er -up and r eset to maintain the device in passwor d pr otection mode . e xecuting the unl ock p assw ord command b y enter ing the corr ect passwor d clears the nonv olatile pr otection bit lock bit, enabling the block nonv olatile pr otection bits to be modified. i f the passwor d pr o vided is incorr ect, the nonv olatile pr otection bit lock bit r emains locked, and the state of the nonv olatile pr otection bits cannot be modified. t o place the device in passwor d pr otection mode , the follo wing two steps ar e r equir ed: f irst, befor e activ ating the passwor d pr otection mode , a 64-bit passwor d must be set and the setting v er ified. p asswor d v er ification is allo w ed only befor e the passwor d pr o- tection mode is activ ated. n ext, passwor d pr otection mode is activ ated b y pr ogr am- ming the passwor d pr otection mode lock bit to 0. this oper ation is irr ev ersible . after the bit is pr ogr ammed, it cannot be er ased, the device r emains per manently in passwor d pr otection mode , and the 64-bit passwor d can be neither r etr iev ed nor r epr ogr ammed. i n addition, all commands to the addr ess wher e the passwor d is stor ed ar e disabled. n ote: ther e is no means to v er ify the passwor d after passwor d pr otection mode is ena- bled. i f the passwor d is lost after enabling the passwor d pr otection mode , ther e is no way to clear the nonv olatile pr otection bit lock bit. passwor d access p asswor d access is a secur ity enhancement that pr otects infor mation stor ed in the main arr ay blocks b y pr ev enting content alter ation or r eads until a v alid 64-bit passwor d is r eceiv ed. p asswor d access may be combined with nonv olatile and/or v olatile pr otection to cr eate a multi-tier ed solution. c ontact y our m icr on sales r epr esentativ e for fur ther details . figur e 13: softwar e pr otection scheme 1 = unprotected (default) 0 = protected 1 = unprotected 0 = protected (default setting depends on the product order option) volatile protection bit nonvolatile protection bit 1 = unlocked (default, after power-up or hardware reset) 0 = locked nonvolatile protection bit lock bit (volatile) nonvolatile protection mode password protection mode volatile protection nonvolatile protection array block 32mb, 64mb, 128mb: 3v embedded parallel nor flash device protection pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 57 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. notes: 1. v olatile protection bits are programmed and cleared individually . nonvolatile protection bits are programmed individually and cleared collectively . 2. once programmed to 0, the nonvolatile protection bit lock bit can be reset to 1 only by taking the device through a power-up or hardware reset. 32mb, 64mb, 128mb: 3v embedded parallel nor flash device protection pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 58 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. common flash interface the common f lash inter face (cfi) is a jedec-appr o v ed, standar diz ed data str uctur e that can be r ead fr om the f lash memor y device . i t allo ws a system's softwar e to quer y the device to deter mine v ar ious electr ical and timing par ameters , density infor mation, and functions suppor ted b y the memor y . the system can inter face easily with the de- vice , enabling the softwar e to upgr ade itself when necessar y . when the read cfi q uer y command is issued, the device enters cfi quer y mode and the data str uctur e is r ead fr om memor y . the follo wing tables sho w the addr esses (a-1, a[7:0]) used to r etr iev e the data. the quer y data is always pr esented on the lo w est or der data outputs (dq[7:0]), and the other data outputs (dq[15:8]) are set to 0. t able 23: query structur e overview note 1 applies to the entire table address subsection name description x16 x8 10h 20h cfi query identification string command set id and algorithm data offset 1bh 36h system interface information device timing and voltage information 27h 4eh device geometry definition flash device layout 40h 80h primary algorithm-specific extended query table additional information specific to the primary al- gorithm (optional) note: 1. query data are always presented on the lowest order data outputs (dq[7:0]). dq[15:8] are set to 0. t able 24: cfi query identification string note 1 applies to the entire table address data description value x16 x8 10h 20h 0051h query unique ascii string "qry" "q" 11h 22h 0052h "r" 12h 24h 0059h "y" 13h 14h 26h 28h 0002h 0000h primary algorithm command set and control interface id code 16-bit id code defining a specific algorithm C 15h 16h 2ah 2ch 0040h 0000h address for primary algorithm extended query table (see the primary algo- rithm-specific extended query table) p = 40h 17h 18h 2eh 30h 0000h 0000h alternate vendor command set and control interface id code second ven- dor-specified algorithm supported C 19h 1ah 32h 34h 0000h 0000h address for alternate algorithm extended query table C note: 1. query data are always presented on the lowest order data outputs (dq[7:0]). dq[15:8] are set to 0. 32mb, 64mb, 128mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 59 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. t able 25: cfi query system interface information note 1 applies to the entire table address data description value x16 x8 1bh 36h 0027h v cc logic supply minimum program/erase voltage bits[7:4] bcd value in volts bits[3:0] bcd value in 100mv 2.7v 1ch 38h 0036h v cc logic supply maximum program/erase voltage bits[7:4] bcd value in volts bits[3:0] bcd value in 100mv 3.6v 1dh 3ah 00b5h v pph (programming) supply minimum program/erase voltage bits[7:4] hex value in volts bits[3:0] bcd value in 100mv 11.5v 1eh 3ch 00c5h v pph (programming) supply maximum program/erase voltage bits[7:4] hex value in volts bits[3:0] bcd value in 100mv 12.5v 1fh 3eh 0004h typical timeout for single byte/word program = 2 n s 16s 20h 40h 0009h typical timeout for maximum size buffer program = 2 n s 512s 21h 42h 0009h typical timeout per individual block erase = 2 n ms 0.5s 22h 44h 000fh typical timeout for full chip erase = 2 n ms 32mb: 33s 0010h 64mb: 66s 0011h 128mb: 131s 23h 46h 0004h maximum timeout for byte/word program = 2 n times typical 256s 24h 48h 0002h maximum timeout for buffer program = 2 n times typical 2048s 25h 4ah 0003h maximum timeout per individual block erase = 2 n times typical 4s 26h 4ch 0002h maximum timeout for chip erase = 2 n times typical 32mb: 131s 0002h 64mb: 262s 0002h 128mb: 524s note: 1. the values in this table are valid for all packages. table 26: device geometry definition address data description value x16 x8 27h 4eh 0016h device size = 2 n in number of bytes 4mb 0017h 8mb 0018h 16mb 28h 29h 50h 52h 0002h 0000h flash device interface code description x8, x16 asynchro- nous 2ah 2bh 54h 56h 0008h 1 0000h maximum number of bytes in multi-byte program or page = 2 n 256 32mb, 64mb, 128mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 60 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 26: device geometry definition (continued) address data description value x16 x8 2ch 58h (see table below) number of erase block regions. it specifies the number of regions containing contiguous erase blocks of the same size. 01h = uniform device 02h = boot device C 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h (see table below) erase block region 1 information bits[15:0] = y , y + 1 = number of identical-size erase blocks bits[31:16] = z, block size in region 1 is z x 256 bytes C 31h 32h 33h 34h 62h 64h 66h 68h (see table below) erase block region 2 information bits[15:0] = y , y + 1 = number of identical-size erase blocks bits[31:16] = z, block size in region 1 is z x 256 bytes C 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information 0 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information 0 note: 1. the value at 2ah in the cfi region is set to 08h (256 bytes) due to compatibility issues. the maximum 256-word program buffer can be used to optimize system program per- formance. table 27: erase block region information address 32mb 64mb 128mb top bottom uniform top bottom uniform uniform 2ch 02h 02h 01h 02h 02h 01h 01h 2dh 07h 07h 3fh 07h 07h 7fh 7fh 2eh 00h 00h 00h 00h 00h 00h 00h 2fh 20h 20h 00h 20h 20h 00h 00h 30h 00h 00h 01h 00h 00h 01h 02h 31h 3eh 3eh 00h 7eh 7eh 00h 00h 32h 00h 00h 00h 00h 00h 00h 00h 33h 00h 00h 00h 00h 00h 00h 00h 34h 01h 01h 00h 01h 01h 00h 00h 32mb, 64mb, 128mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 61 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. t able 28: primary algorithm-specific extended query t able note 1 applies to the entire table address data description value x16 x8 40h 80h 0050h primary algorithm extended query table unique ascii string pri "p" 41h 82h 0052h "r" 42h 84h 0049h "i" 43h 86h 0031h major version number, ascii "1" 44h 88h 0033h minor version number, ascii "3" 45h 8ah 0018h address sensitive unlock (bits[1:0]): 00 = required 01 = not required silicon revision number (bits[7:2]) required 46h 8ch 0002h erase suspend: 00 = not supported 01 = read only 02 = read and write 2 47h 8eh 0001h block protection: 00 = not supported x = number of blocks per group 1 48h 90h 0000h t emporary block unprotect: 00 = not supported 01 = supported not supported 49h 92h 0008h block protect/unprotect: 08 = m29ewh/m29ewl 8 4ah 94h 0000h simultaneous operations: not supported n/a 4bh 96h 0000h burst mode: 00 = not supported 01 = supported not supported 4ch 98h 0002h page mode: 00 = not supported 01 = 8-word page 02 = 8-word page 03 = 16-word page 8-word page 4dh 9ah 00b5h v pph supply minimum program/erase voltage: bits[7:4] hex value in volts bits[3:0] bcd value in 100mv 11.5v 4eh 9ch 00c5h v pph supply maximum program/erase voltage: bits[7:4] hex value in volts bits[3:0] bcd value in 100mv 12.5v 32mb, 64mb, 128mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 62 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. t able 28: primary algorithm-specific extended query t able (continued) note 1 applies to the entire table address data description value x16 x8 4fh 9eh 00xxh t op/bottom boot block flag: xx = 02h: bottom boot device, hw protection for bottom two blocks xx = 03h: t op boot device, hw protection for top two blocks xx = 04h: uniform device, hw protection for lowest block xx = 05h: uniform device, hw protection for highest block device type (bot- tom boot, top boot, uniform) 50h a0h 0001h program suspend: 00 = not supported 01 = supported supported note: 1. the values in this table are valid for both packages. 32mb, 64mb, 128mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 63 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. power-up and reset characteristics table 29: power-up specifications parameter symbol min unit notes legacy jedec v cc high to v ccq high C t vchvcqh 0 s 1 v cc high to rising edge of rst# t vcs t vchph 60 s 2 v ccq high to rising edge of rst# t vios t vcqhph 0 s 2 rst# high to chip enable low t rh t phel 50 ns rst# high to write enable low C t phwl 150 ns notes: 1. v cc and v ccq ramps must be synchronized during power -up. 2. if rst# is not stable for t vcs or t vios, the device will not allow any read or write oper - ations, and a hardware reset is required. figur e 14: power -up timing t rh t vios t vcs t phwl t vchvcqh v ccq v cc ce# rst# we# 32mb, 64mb, 128mb: 3v embedded parallel nor flash power-up and reset characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 64 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 30: reset ac specifications condition/parameter symbol min max unit notes legacy jedec rst# low to read mode during program or erase t ready t plrh C 25 s 1 rst# pulse width t rp t plph 100 C ns rst# high to ce# low, oe# low t rh t phel, t phgl 50 C ns 1 rst# low to standby mode during read mode t rpd C 10 C s rst# low to standby mode during program or erase 50 C s ry/by# high to ce# low, oe# low t rb t rhel, t rhgl 0 C ns 1 note: 1. sampled only; not 100% tested. figur e 15: reset ac timing C no program/erase operation in pr ogr ess t rh ry/by# ce#, oe# rst# t rp figur e 16: reset ac timing during program/erase operation t rb ry/by# ce#, oe# rst# t rp t rh t ready 32mb, 64mb, 128mb: 3v embedded parallel nor flash power-up and reset characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 65 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. absolute ratings and operating conditions stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions outside those indicated in the operational sections of this specification is not im- plied. exposure to absolute maximum rating conditions for extended periods may ad- versely affect reliability. table 31: absolute maximum/minimum ratings parameter symbol min max units notes temperature under bias t bias C40 85 c storage temperature t stg C65 125 c input/output voltage v io C0.6 v cc + 0.6 v 1, 2 supply voltage v cc C2 5.6 v 1, 2 input/output supply voltage v ccq C2 5.6 v 1, 2 program voltage v pph C2 14.5 v 1, 2, 3 notes: 1. during signal transitions, minimum voltage may undershoot to ?2v during periods less than 20ns. 2. during signal transitions, maximum voltage may overshoot to v cc + 2v for periods less than 20ns. 3. v pph must not remain at 12v for more than 80 hours cumulative. table 32: operating conditions parameter symbol min max unit supply voltage v cc 2.7 3.6 v input/output supply voltage (v ccq v cc ) v ccq 1.65 3.6 v program voltage v pp C0.6 12.5 v ambient operating temperature t a C40 85 c load capacitance c l 30 pf input rise and fall times C C 2.5 ns input pulse voltages C 0 to v ccq v input and output timing reference voltages C v ccq /2 v 32mb, 64mb, 128mb: 3v embedded parallel nor flash absolute ratings and operating conditions pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 66 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 17: ac measur ement load cir cuit c l v ccq 25k device under test 0.1f v cc 0.1f v pp 25k note: 1. c l includes jig capacitance. figur e 18: ac measur ement i/o w aveform v ccq 0v v ccq /2 table 33: input/output capacitance parameter symbol test condition min max unit input capacitance c in v in = 0v 2 7 pf output capacitance c out v out = 0v 2 5 pf 32mb, 64mb, 128mb: 3v embedded parallel nor flash absolute ratings and operating conditions pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 67 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. dc characteristics table 34: dc current characteristics parameter symbol conditions min typ max unit notes input leakage current i li 0v v in v cc C C 1 a 1 output leakage current i lo 0v v out v cc C C 1 a v cc read current random read i cc1 ce# = v il , oe# = v ih , f = 5 mhz C 20 25 ma page read ce# = v il , oe# = v ih , f = 13 mhz C 12 16 ma v cc standby current 128mb i cc2 ce# = v ccq 0.2v, rst# = v ccq 0.2v C 50 120 a 64mb C 35 120 a 32mb C 35 120 a v cc program/erase/blank check current i cc3 program/ erase controller active v pp /wp# = v il or v ih C 35 50 ma 2 v pp /wp# = v pph C 26 33 ma v pp current read i pp1 v pp /wp# v cc C 2 15 a standby C 0.2 5 a reset i pp2 rst# = v ss 0.2v C 0.2 5 a program operation ongoing i pp3 v pp /wp# = 12v 5% C 5 10 ma v pp /wp# = v cc C 0.05 0.10 ma erase operation ongoing i pp4 v pp /wp# = 12v 5% C 5 10 ma v pp /wp# = v cc C 0.05 0.10 ma notes: 1. the maximum input leakage current is 5a on the v pp /wp# pin. 2. sampled only; not 100% tested. 32mb, 64mb, 128mb: 3v embedded parallel nor flash dc characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 68 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 35: dc voltage characteristics parameter symbol conditions min typ max unit notes input low voltage v il v cc 2.7v C0.5 C 0.8 v input high voltage v ih v cc 2.7v v ccq C0.4 C v ccq +0.5 v 1 output low voltage v ol i ol = 100a, v cc = v cc,min , v ccq = v ccq,min C C 0.2 v output high voltage v oh i oh = 100a, v cc = v cc,min , v ccq = v ccq,min v ccq - 0.2 C C v voltage for v pp /wp# program acceleration v pph C 11.5 C 12.5 v v pp logic level v ppl 2.7 C 3.6 v program/erase lockout supply voltage v lko C 2.3 C C v 2 notes: 1. if v ccq range is 2.7v~3.6v, v ih min is 2v. 2. sampled only; not 100% tested. 32mb, 64mb, 128mb: 3v embedded parallel nor flash dc characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 69 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. read ac characteristics table 36: read ac characteristics parameter symbol condition package min max unit notes legacy jedec address valid to next address valid t rc t avav ce# = v il , oe# = v il bga 60 C ns tsop 70 C ns address valid to output valid t acc t avqv ce# = v il , oe# = v il bga C 60 ns tsop C 70 ns address valid to output valid (page) t page t avqv1 ce# = v il , oe# = v il bga C 25 ns tsop C 25 ns ce# low to output transition t lz t elqx oe# = v il bga 0 C ns 1 tsop 0 C ns 1 ce# low to output valid t e t elqv oe# = v il bga C 60 ns tsop C 70 ns oe# low to output transition t olz t glqx ce# = v il bga 0 C ns 1 tsop 0 C ns 1 oe# low to output valid t oe t glqv ce# = v il bga C 25 ns tsop C 25 ns ce# high to output high-z t hz t ehqz oe# = v il bga C 20 ns 1 tsop C 20 ns 1 oe# high to output high-z t df t ghqz ce# = v il bga C 15 ns 1 tsop C 15 ns 1 ce#, oe#, or address transition to output transition t oh t ehqx, t ghqx, t axqx C bga 0 C ns tsop 0 C ns ce# to byte# low t elfl t elbl C bga C 10 ns tsop C 10 ns ce# to byte# high t elfh t elbh C bga C 10 ns tsop C 10 ns byte# low to output valid t flqv t blqv C bga C 1 s tsop C 1 s byte# high to output valid t fhqv t bhqv C bga C 1 s tsop C 1 s byte# low to output in high-z t flqz t blqz C bga C 1 s tsop C 1 s note: 1. sampled only; not 100% tested. 32mb, 64mb, 128mb: 3v embedded parallel nor flash read ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 70 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 19: random read ac timing (8-bit mode) valid valid t acc t rc t oh t e t elfl t flqz t lz t oh t hz t olz t oh t oe t df a[max:0]/a-1 ce# oe# dq[7:0] byte# figur e 20: random read ac timing (16-bit mode) valid valid t acc t rc t oh t e t elfh t lz t oh t hz t olz t oh t oe t df a[max:0] ce# oe# dq[15:0] byte# 32mb, 64mb, 128mb: 3v embedded parallel nor flash read ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 71 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 21: byte# t ransition read ac timing data-out data-out valid valid t acc t oh t fhqv t blqx high-z a[max:0] aC1 byte# dq[7:0] dq[15:8] figur e 22: page read ac timing (16-bit mode) valid valid valid valid valid valid valid valid t acc t e t page t oh t hz t oh t oe t df a[max:4] a[3:0] ce# oe# dq[15:0] valid valid valid valid valid valid valid note: 1. page size is 8 words (16 bytes) and is addressed by address inputs a[2:0] in x16 bus mode and a[2:0] plus dq15/a?1 in x8 bus mode. 32mb, 64mb, 128mb: 3v embedded parallel nor flash read ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 72 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. write ac characteristics table 37: we#-controlled write ac characteristics parameter symbol package min typ max unit notes legacy jedec address valid to next address valid t wc t avav bga 60 C C ns tsop 70 C C ns ce# low to we# low t cs t elwl bga 0 C C ns tsop 0 C C ns we# low to we# high t wp t wlwh bga 35 C C ns tsop 35 C C ns input valid to we# high t ds t dvwh bga 30 C C ns tsop 30 C C ns we# high to input transition t dh t whdx bga 0 C C ns tsop 0 C C ns we# high to ce# high t ch t wheh bga 0 C C ns tsop 0 C C ns we# high to we# low t wph t whwl bga 20 C C ns tsop 20 C C ns address valid to we# low t as t avwl bga 0 C C ns tsop 0 C C ns we# low to address transition t ah t wlax bga 45 C C ns tsop 45 C C ns oe# high to we# low C t ghwl bga 0 C C ns tsop 0 C C ns we# high to oe# low t oeh t whgl bga 0 C C ns tsop 0 C C ns program/erase valid to ry/by# low t busy t whrl bga C C 90 ns 1 tsop C C 90 ns 1 v cc high to ce# low t vcs t vchel bga 60 C C s tsop 60 C C s note: 1. sampled only; not 100% tested. 32mb, 64mb, 128mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 73 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 23: we#-contr olled pr ogram ac timing (8-bit mode) aaah pa pa 3rd cycle 4th cycle read cycle data polling t wc t wc t as t wp t ds t whwh1 t df t wph t ah t e t cs t ghwl t oe t dh t oh t ch a[max:0]/a-1 ce# oe# we# dq[7:0] aoh pd dq7# d out d out notes: 1. only the third and fourth cycles of the program command are represented. the pro- gram command is followed by checking of the status register data polling bit and by a read operation that outputs the data (d out ) programmed by the previous program command. 2. p a is the address of the memory location to be programmed. pd is the data to be pro- grammed. 3. dq7 is the complement of the data bit being programmed to dq7 (see data polling bit [dq7]). 4. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 32mb, 64mb, 128mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 74 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 24: we#-contr olled pr ogram ac timing (16-bit mode) 555h pa pa 3rd cycle 4th cycle read cycle data polling t wc t wc t as t wp t ds t df t whwh1 t wph t ah t e t cs t ghwl t oe t dh t oh t ch a[max:0] ce# oe# we# dq[15:0] aoh pd dq7# d out d out notes: 1. only the third and fourth cycles of the program command are represented. the pro- gram command is followed by checking of the status register data polling bit and by a read operation that outputs the data (d out ) programmed by the previous program command. 2. p a is the address of the memory location to be programmed. pd is the data to be pro- grammed. 3. dq7 is the complement of the data bit being programmed to dq7 (see data polling bit [dq7]). 4. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 32mb, 64mb, 128mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 75 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 38: ce#-controlled write ac characteristics parameter symbol package min typ max unit legacy jedec address valid to next address valid t wc t avav bga 60 C C ns tsop 70 C C ns we# low to ce# low t ws t wlel bga 0 C C ns tsop 0 C C ns ce# low to ce# high t cp t eleh bga 35 C C ns tsop 35 C C ns input valid to ce# high t ds t dveh bga 30 C C ns tsop 30 C C ns ce# high to input transition t dh t ehdx bga 0 C C ns tsop 0 C C ns ce# high to we# high t wh t ehwh bga 0 C C ns tsop 0 C C ns ce# high to ce# low t cph t ehel bga 20 C C ns tsop 20 C C ns address valid to ce# low t as t avel bga 0 C C ns tsop 0 C C ns ce# low to address transition t ah t elax bga 45 C C ns tsop 45 C C ns oe# high to ce# low C t ghel bga 0 C C ns tsop 0 C C ns 32mb, 64mb, 128mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 76 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 25: ce#-contr olled pr ogram ac timing (8-bit mode) aaah pa pa 3rd cycle 4th cycle data polling t wc t as t cp t ds t whwh1 t cph t ah t ws t ghel t dh t wh a[max:0]/a-1 we# oe# ce# dq[7:0] aoh pd dq7# d out notes: 1. only the third and fourth cycles of the program command are represented. the pro- gram command is followed by checking of the status register data polling bit. 2. p a is the address of the memory location to be programmed. pd is the data to be pro- grammed. 3. dq7 is the complement of the data bit being programmed to dq7 (see data polling bit [dq7]). 4. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 32mb, 64mb, 128mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 77 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 26: ce#-contr olled pr ogram ac timing (16-bit mode) 555h pa pa 3rd cycle 4th cycle data polling t wc t as t cp t ds t whwh1 t cph t ah t ws t ghel t dh t wh a[max:0] we# oe# ce# dq[15:0] aoh pd dq7# d out notes: 1. only the third and fourth cycles of the program command are represented. the pro- gram command is followed by checking of the status register data polling bit. 2. p a is the address of the memory location to be programmed. pd is the data to be pro- grammed. 3. dq7 is the complement of the data bit being programmed to dq7 (see data polling bit [dq7]). 4. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 32mb, 64mb, 128mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 78 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 27: chip/block erase ac timing (8-bit mode) aaah t wc t as t wp t ds t wph t ah t cs t ghwl t dh t ch a[max:0]/ aC1 ce# oe# we# dq[7:0] aah 555h aaah aaah bah 1 555h aaah 55h 55h aah 80h 10h/ 30h notes: 1. for a chip erase command, the address is 555h, and the data is 10h; for a block erase command, the address is bad, and the data is 30h. 2. bad is the block address. 3. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 32mb, 64mb, 128mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 79 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. accelerated program, data polling/toggle ac characteristics table 39: accelerated program and data polling/data toggle ac characteristics parameter symbol min max unit legacy jedec v pp /wp# rising or falling time C t vhvpp 250 C ns valid v hh on v pp /wp# to we# high C t vhhwh 50 C ns address setup time to oe# low during toggle bit polling t aso t axgl 15 C ns address hold time from oe# during toggle bit polling t aht t ghax, t ehax 0 C ns ce# high during toggle bit polling t eph t ehel2 20 C ns output hold time during data and toggle bit polling t oeh t whgl2, t ghgl2 20 C ns program/erase valid to ry/by# low t busy t whrl C 90 ns note: 1. sampled only; not 100% tested. figur e 28: accelerated pr ogram ac timing t vhvpp t vhvpp v pph v il or v ih v pp /wp# figur e 29: data polling ac timing dq7# data dq7# valid dq7 data output flag data output flag valid dq[6:0] data t hz/ t df t e t oe t ch t busy t oeh ce# oe# we# dq[6:0] dq7 ry/by# 32mb, 64mb, 128mb: 3v embedded parallel nor flash accelerated program, data polling/toggle ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 80 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. notes: 1. dq7 returns a valid data bit when the program or erase command has completed. 2. see the following tables for timing details: read ac characteristics, accelerated pro- gram and data polling/data t oggle ac characteristics. figur e 30: t oggle/alter native t oggle bit polling ac timing (8-bit mode) toggle toggle toggle data stop toggling output valid t busy t oeh t eph t oeh ce# we# oe# dq6/dq2 ry/by# t oeh t aht t aso t aht t dh t as a[max:0]/ aC1 t oe t e notes: 1. dq6 stops toggling when the program or erase command has completed. dq2 stops toggling when the chip erase or block erase command has completed. 2. see the following tables for timing details: read ac characteristics, accelerated pro- gram and data polling/data toggle ac characteristics. 32mb, 64mb, 128mb: 3v embedded parallel nor flash accelerated program, data polling/toggle ac characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 81 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. electrical specifications C program/erase characteristics table 40: program/erase characteristics parameter buffer size byte word min typ 1, 2 max 2 unit block erase C C C C 0.5 4 s erase suspend latency C C C C 20 25 s block erase timeout C C C 50 C C s byte program single-byte program C C C C 15 175 s double-/ quadruple-/ octuple-byte program C C C C 10 200 s byte write to buffer program 32 32 C C 70 200 s 64 64 C C 85 200 s 256 256 C C 160 710 s ef fective write to buf fer program per byte 32 1 C C 2.19 6.25 s 64 1 C C 1.33 3.125 s 256 1 C C 0.625 2.77 s word program single-word program C C C C 15 175 s word write to buffer program 16 C 16 C 70 200 s 32 C 32 C 85 200 s 128 C 128 C 160 710 s 256 C 256 C 284 1280 s full buffer program with v pph 256 C 256 C 160 800 s ef fective write to buf fer program per word 16 C 1 C 4.375 12.5 s 32 C 1 C 2.66 6.25 s 128 C 1 C 1.25 5.55 s 256 C 1 C 1.11 5 s effective full buffer program per word with v pph 256 C 1 C 0.625 3.125 s program suspend latency C C C C 20 25 s blank check C C C C 3.2 C ms program/erase cycles (per block) C C C 100,000 C C cycles notes: 1. typical values measured at room temperature and nominal voltages. 2. sampled, but not 100% tested. 32mb, 64mb, 128mb: 3v embedded parallel nor flash electrical specifications C program/erase characteristics pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 82 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. package dimensions figur e 31: 56-pin tsop C 14mm x 20mm see detail a 0.50 typ 14.00 0.10 1.20 max 18.40 0.10 20.00 0.20 1.00 0.05 0.10 0.05 0.22 0.05 detail a 0.50 0.10 3 typ/ 5 max 0.10 0.10 min/ 0.21 max pin #1 notes: 1. all dimensions are in millimeters. 2. for the lead width value of 0.22 0.05, there is also a legacy value of 0.15 0.05. 32mb, 64mb, 128mb: 3v embedded parallel nor flash package dimensions pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 83 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 32: 48-pin tsop C 12mm x 20mm die 1 24 48 25 0.50 typ 0.10 max 0.10 min/ 0.21 max 0.60 + 0.10 + 3 o 2 o 3 o 0.22 + 0.05 0.10 + 0.05 1.20 max 1.00 + 0.05 0.80 typ 20.00 + 0.20 18.40 + 0.10 12.00 + 0.10 note: 1. all dimensions are in millimeters. 32mb, 64mb, 128mb: 3v embedded parallel nor flash package dimensions pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 84 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 33: 48-ball bga C 6mm x 8mm ball a1 5.60 typ 1.00 max 0.64 typ 0.10 max 0.20 min 1.00 typ 0.40 typ 4.00 typ 0.40 typ 1.20 typ 0.80 typ 0.80 typ 8.00 + 0.10 0.35 + 0.5 6.00 + 0.10 note: 1. all dimensions are in millimeters. 32mb, 64mb, 128mb: 3v embedded parallel nor flash package dimensions pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 85 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figur e 34: 64-ball fortified bga C 11mm x 13mm seating plane 0.80 typ 0.10 13.00 0.10 0.60 0.05 1.00 typ 3.00 typ a b c d e f g h 7.00 typ 1.40 max ball a1 id 1.00 typ 2.00 typ 0.49 typ/ 0.40 min 11.00 0.10 7.00 typ 64x 8 7 6 5 4 3 2 1 note: 1. all dimensions are in millimeters. 32mb, 64mb, 128mb: 3v embedded parallel nor flash package dimensions pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 86 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. revision history rev . b C 11/12 ? a dded text to s ignal d escr iptions to clar ify v pp /wp# and vss decoupling r equir e- ment. ? a dded note to dc v oltage char acter istics table to clar ify vih spec . rev . a C 08/12 ? initial micron rebrand release 8000 s. federal w ay , p .o. box 6, boise, id 83707-0006, t el: 208-368-3900 www .micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron t echnology , inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 32mb, 64mb, 128mb: 3v embedded parallel nor flash revision history pdf: 09005aef84dc44a7 m29ew_32mb-128mb.pdf - rev. b 11/12 en 87 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. |
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